An evolutionary approach for reducing the energy in address buses

ABSTRACT

In this paper we present a genetic approach for the efficient generation of an encoder to minimize switching activity on the high-capacity lines of a communication bus. The approach is a static one in the sense that the encoder is realized ad hoc according to the traffic on the bus. This is not, however, a limiting hypothesis if the application scenario considered is that of embedded systems. An embedded system, in fact, executes the same application throughout its lifetime and so it is possible to have detailed knowledge of the trace of the patterns transmitted on a bus following execution of a specific application. The approach is compared with the most efficient encoding schemes proposed in the literature on both multiplexed and separate buses. The results obtained demonstrate the validity of the approach, which on average saves up to 50% of the transitions normally required.

REFERENCES

• 1: Neil H. West and Kamran Eshraghian, Principles of CMOS VLSI Design, Addison Wesley, 1998.
• 2: Pinaki Mazumder , Elizabeth M. Rudnick, Genetic algorithms for VLSI design, layout & test automation, Prentice Hall PTR, Upper Saddle River, NJ, 1999
• 3: Luca Benini , Giovanni De Mecheli , Enrico Macii , Massimo Poncino , Stefano Quer, Power optimization of core-based systems by address bus encoding, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.4, p.554-562, Dec. 1998 [doi>10.1109/92.736127]
• 4: Ching-Long Su , Chi-Ying Tsui , Alvin M. Despain, Saving Power in the Control Path of Embedded Processors, IEEE Design & Test, v.11 n.4, p.24-30, October 1994 [doi>10.1109/54.329448]
• 5: Luca Benini , Giovanni de Micheli , Enrico Macii , Donatella Sciuto , Cristina Silvano, Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems, Proceedings of the 7th Great Lakes Symposium on VLSI, p.77, March 13-15, 1997
• 6: Mircea R. Stan , Wayne P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.1, p.49-58, March 1995 [doi>10.1109/92.365453]
• 7: L. Benini , G. De Micheli , E. Macii , D. Sciuto , C. Silvano, Address bus encoding techniques for system-level power optimization, Proceedings of the conference on Design, automation and test in Europe, p.861-867, February 23-26, 1998, Le Palais des Congrés de Paris, France