Efficient Memory Integrity Verification and Encryption for Secure Processors

ABSTRACT

Secure processors enable new sets of applications suchas commercial grid computing, software copy-protection,and secure mobile agents by providing security from bothphysical and software attacks. This paper proposes newhardware mechanisms for memory integrity verification andencryption, which are two key primitives required in single-chipsecure processors. The integrity verification mechanismoffers significant performance advantages over existingones when the checks are infrequent as in grid computingapplications. The encryption mechanism improves theperformance in all cases.

REFERENCES

• 1: Ross J. Anderson, Security Engineering: A Guide to Building Dependable Distributed Systems, John Wiley & Sons, Inc., New York, NY, 2001
• 2: Manuel Blum , Will Evans , Peter Gemmell , Sampath Kannan , Moni Naor, Checking the correctness of memories, Proceedings of the 32nd annual symposium on Foundations of computer science, p.90-99, September 1991, San Juan, Puerto Rico [doi>10.1109/SFCS.1991.185352]
• 3: [3] D. Burger and T. M. Austin. The SimpleScalar Tool Set, Version 2.0. Technical report, University of Wisconsin-Madison Computer Science Department, 1997.
• 4: [4] A. Carroll, M. Juarez, J. Polk, and T. Leininger. Microsoft "Palladium": A Business Overview. In Microsoft Content Security Business Unit, August 2002.
• 5: Joris Claessens , Bart Preneel , Joos Vandewalle, (How) can mobile agents do secure electronic transactions on untrusted hosts? A survey of the security issues and the current solutions, ACM Transactions on Internet Technology (TOIT), v.3 n.1, p.28-48, February 2003 [doi>10.1145/643477.643479]
• 6: [6] D. Clarke, S. Devadas, M. van Dijk, B. Gassend, and G. E. Suh. Incremental multiset hash functions and their application to memory integrity checking. In Asiacrypt 2003 Proceedings , November 2003.
• 7: D. Eastlake, 3rd , P. Jones, US Secure Hash Algorithm 1 (SHA1), RFC Editor, 2001
• 8: Blaise Gassend , Dwaine Clarke , Marten van Dijk , Srinivas Devadas, Silicon physical random functions, Proceedings of the 9th ACM conference on Computer and communications security, November 18-22, 2002, Washington, DC, USA [doi>10.1145/586110.586132]
• 9: Blaise Gassend , G. Edward Suh , Dwaine Clarke , Marten van Dijk , Srinivas Devadas, Caches and Hash Trees for Efficient Memory Integrity Verification, Proceedings of the 9th International Symposium on High-Performance Computer Architecture, p.295, February 08-12, 2003
• 10: John L. Henning, SPEC CPU2000: Measuring CPU Performance in the New Millennium, Computer, v.33 n.7, p.28-35, July 2000 [doi>10.1109/2.869367]
• 11: Henry Kuo , Ingrid Verbauwhede, Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm, Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems, p.51-64, May 14-16, 2001
• 12: David Lie Chandramohan Thekkath , Mark Mitchell , Patrick Lincoln , Dan Boneh , John Mitchell , Mark Horowitz, Architectural support for copy and tamper resistant software, Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, p.168-177, November 2000, Cambridge, Massachusetts, United States
• 13: [13] H. Lipmaa, P. Rogaway, and D. Wagner. Comments to NIST concerning AES-modes of operations: CTR-mode encryption. In Symmetric Key Block Cipher Modes of Operation Workshop, Baltimore, Maryland, USA, 2000.
• 14: [14] R. C. Merkle. Protocols for public key cryptography. In IEEE Symposium on Security and Privacy, pages 122-134, 1980.
• 15: J. Naor , M. Naor, Small-bias probability spaces: efficient constructions and applications, Proceedings of the twenty-second annual ACM symposium on Theory of computing, p.213-223, May 13-17, 1990, Baltimore, Maryland, United States [doi>10.1145/100216.100244]
• 16: [16] N. I. of Science and Technology. FIPS PUB 197: Advanced Encryption Standard (AES), November 2001.
• 17: R. Rivest, The MD5 Message-Digest Algorithm, RFC Editor, 1992
• 18: [18] R. L. Rivest. The RC5 Encryption Algorithm, from Dr. Dobb's Journal, January, 1995. In William Stallings, Practical Cryptography for Data Internetworks, IEEE Computer Society Press, 1996. 1996.
• 19: Patrick R. Schaumont , Henry Kuo , Ingrid M. Verbauwhede, Unlocking the design secrets of a 2.29 Gb/s Rijndael processor, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514079]
• 20: Sean W. Smith , Steve Weingart, Building a high-performance, programmable secure coprocessor, Computer Networks: The International Journal of Computer and Telecommunications Networking, v.31 n.9, p.831-860, April 23, 1999
• 21: G. Edward Suh , Dwaine Clarke , Blaise Gassend , Marten van Dijk , Srinivas Devadas, AEGIS: architecture for tamper-evident and tamper-resistant processing, Proceedings of the 17th annual international conference on Supercomputing, June 23-26, 2003, San Francisco, CA, USA [doi>10.1145/782814.782838]
• 22: [22] B. S. Yee. Using Secure Coprocessors. PhD thesis, Carnegie Mellon University, 1994.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS
      C.2.0 General
          Subjects: Security and protection (e.g., firewalls)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware; Memory technologies

General Terms:
Design, Performance, Reliability, Security