Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice

ABSTRACT

On-ine Transaction Processing (OLTP) workloads arecrucial benchmarks for the design and analysis of serverprocessors. Typical cached configurations used byresearchers to simulate OLTP workloads are orders ofmagnitude smaller than the fully scaled configurationsused by OEM vendors to achieve world-record transactionprocessing throughput. The objective of this study is todiscover the underlying relationships that characterizeOLTP performance over a wide range of configurations.To this end, we have derived the "iron law" of databaseperformance. Using our iron law, we show that both theaverage instructions executed per transaction (IPX) andthe average cycles per instruction (CPI) are critical to thetransaction-throughput performance. We use an extensive,empirical examination of an Oracle® based commercialOLTP workload on an Intel® XeonTM multiprocessorsystem to characterize the scaling behavior of both theIPX and the CPI. We demonstrate that across a widerange of configurations the IPX and CPI behavior followspredictable trends, which can be accurately characterizedby simple linear or piece-wise linear approximations.Based on our data,we propose a method for selecting aminimal, representative workload configuration fromwhich behaviors of much larger OLTP configurations canbe accurately extrapolated.

REFERENCES

• 1: Anastassia Ailamaki , David J. DeWitt , Mark D. Hill , David A. Wood, DBMSs on a Modern Processor: Where Does Time Go?, Proceedings of the 25th International Conference on Very Large Data Bases, p.266-277, September 07-10, 1999
• 2: Alaa R. Alameldeen , David A. Wood, Variability in Architectural Simulations of Multi-Threaded Workloads, Proceedings of the 9th International Symposium on High-Performance Computer Architecture, p.7, February 08-12, 2003
• 3: Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors, Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02), p.242, September 16-18, 2002
• 4: [4] T. Diep, M. Annavaram, H. Nueckel, B. Hirano, and J.P. Shen. Analyzing Performance Characteristics of OLTP Cached Workloads by Linear Interpolation. In Proceedings of the 6th Workshop on Computer Architecture Evaluation using Commercial Workloads, pages 51-59, February 2003.
• 5: Luiz André Barroso , Kourosh Gharachorloo , Edouard Bugnion, Memory system characterization of commercial workloads, Proceedings of the 25th annual international symposium on Computer architecture, p.3-14, June 27-July 02, 1998, Barcelona, Spain
• 6: Luiz André Barroso , Kourosh Gharachorloo , Robert McNamara , Andreas Nowatzyk , Shaz Qadeer , Barton Sano , Scott Smith , Robert Stets , Ben Verghese, Piranha: a scalable architecture based on single-chip multiprocessing, Proceedings of the 27th annual international symposium on Computer architecture, p.282-293, June 2000, Vancouver, British Columbia, Canada
• 7: [7] L.A. Barroso, K. Gharachorloo, A. Nowatzyk, and B. Verghese. Impact of Chip-Level Integration on Performance of OLTP Workloads. In Proceedings of the 6th International Symposium on High-Performance Computer Architecture, pages 3-14, January 2000.
• 8: Z. Cvetanovic , D. Bhandarkar, Characterization of alpha AXP performance using TP and SPEC workloads, Proceedings of the 21st annual international symposium on Computer architecture, p.60-70, April 18-21, 1994, Chicago, Illinois, United States
• 9: Jack L. Lo , Luiz André Barroso , Susan J. Eggers , Kourosh Gharachorloo , Henry M. Levy , Sujay S. Parekh, An analysis of database workload performance on simultaneous multithreaded processors, Proceedings of the 25th annual international symposium on Computer architecture, p.39-50, June 27-July 02, 1998, Barcelona, Spain
• 10: M. T. Franklin , W. P. Alexander , R. Jauhari , A. M. G. Maynard , B. R. Olszewski, Commercial workload performance in the IBM POWER2 RISC System/6000 processor, IBM Journal of Research and Development, v.38 n.5, p.555-561, Sept. 1994
• 11: [11] J. Kahle. Power4: A Dual-CPU Processor Chip. Microprocessor Forum '99, October 1999.
• 12: Kimberly Keeton , David A. Patterson , Yong Qiang He , Roger C. Raphael , Walter E. Baker, Performance characterization of a Quad Pentium Pro SMP using OLTP workloads, Proceedings of the 25th annual international symposium on Computer architecture, p.15-26, June 27-July 02, 1998, Barcelona, Spain
• 13: [13] J. Shen and M. Lipasti, Modern Processor Design: Fundamentals of Superscalar Processors, McGraw Hill, 2002.
• 14: [14] The IA-32 Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide.
• 15: [15] The Intel VTune Performance Analyzer. http://www.intel.com/software/products/vtune/.
• 16: [16] The Intel Xeon Processor MP Product Overview. http://developer.intel.com/design/Xeon/xeonmp/prodb ref/.
• 17: Kunle Olukotun , Basem A. Nayfeh , Lance Hammond , Ken Wilson , Kunyung Chang, The case for a single-chip multiprocessor, Proceedings of the seventh international conference on Architectural support for programming languages and operating systems, p.2-11, October 01-04, 1996, Cambridge, Massachusetts, United States
• 18: Parthasarathy Ranganathan , Kourosh Gharachorloo , Sarita V. Adve , Luiz André Barroso, Performance of database workloads on shared-memory systems with out-of-order processors, Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, p.307-318, October 02-07, 1998, San Jose, California, United States
• 19: M. Rosenblum , E. Bugnion , S. A. Herrod , E. Witchel , A. Gupta, The impact of architectural trends on operating system performance, Proceedings of the fifteenth ACM symposium on Operating systems principles, p.285-298, December 03-06, 1995, Copper Mountain, Colorado, United States
• 20: [20] Standard Performance Council. The SPEC95 CPU Benchmark Suite. http://www.spec.org/cpu2000.
• 21: [21] K. Keeton, D.A. Patterson. The impact of Hardware and Software Configuration on Computer Architecture Performance Evaluation. In the first Workshop on Computer Architecture Evaluation using Commercial Workloads.
• 22: [22] R. Hankins, M. Annavaram, T. Diep, H. Eri, B. Hirano, H. Nueckel, and J.P. Shen. Comparing and Contrasting OLTP Workload Scaling on IA32 and IPF. October 2003. http://www.intel.com/research.

INDEX TERMS

Primary Classification:
  H. Information Systems
  H.2 DATABASE MANAGEMENT
      H.2.4 Systems
          Subjects: Transaction processing

Additional Classification:
  D. Software
  D.4 OPERATING SYSTEMS
      D.4.8 Performance
          Subjects: Simulation; Operational analysis

  K. Computing Milieux
  K.6 MANAGEMENT OF COMPUTING AND INFORMATION SYSTEMS
      K.6.2 Installation Management
          Subjects: Benchmarks; Performance and usage measurement

General Terms:
Management, Performance