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Exploiting bank locality in multi-bank memories
Source International Conference on Compilers, Architecture and Synthesis for Embedded Systems archive
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems table of contents
San Jose, California, USA
SESSION: Memory hierarchy table of contents
Pages: 287 - 297  
Year of Publication: 2003
ISBN:1-58113-676-5
Authors
G. Chen  The Pennsylvania State University
M. Kandemir  The Pennsylvania State University
H. Saputra  The Pennsylvania State University
M. J. Irwin  The Pennsylvania State University
Sponsors
ACM: Association for Computing Machinery
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
ACM  New York, NY, USA
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ABSTRACT

Bank locality can be defined as localizing the number of load/store accesses to a small set of memory banks at a given time. An optimizing compiler can modify a given input code to improve its bank locality. There are several practical advantages of enhancing bank locality, the most important of which is reduced memory energy consumption. Recent trends indicate that energy consumption is fast becoming a first-order design parameter as processor-based systems continue to become more complex and multi-functional. Off-chip memory energy consumption in particular can be a limiting factor in many embedded system designs. This paper presents a novel compiler-based strategy for maximizing the benefits of low-power operating modes available in some recent DRAM-based multi-bank memory systems. In this strategy, the compiler uses linear algebra to represent and optimize bank locality in a mathematical framework. We discuss that exploiting bank locality can be cast as loop (iteration space) and array layout (data space) transformations. We also present experimental data showing the effectiveness of our optimization strategy. Our results show that exploiting bank locality can result in large energy savings.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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X. Fan, C. S. Ellis, and A. R. Lebeck. Modeling of DRAM Power Control Policies Using Deterministic and Stochastic Petri Nets. In Proc. Workshop on Power-Aware Computer Systems, Springer-Verlag, February 2002.
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A. Farrahi, G. Tellez, and M. Sarrafzadeh. Exploiting Sleep Mode for Memory Partitions and Other Applications. VLSI Design, Vol. 7, No. 3, pp. 271--287.
 
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W-M. W. Hwu. Embedded Microprocessor Comparison. http://www.crhc.uiuc.edu/IMPACT/ece412/public_html/Notes/412_lec1/ppframe.htm.
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S. -T. Leung and J. Zahorjan. Optimizing Data Locality by Array Restructuring. Technical Report TR 95-09-01, Dept. of Computer Science and Engineering, University of Washington, September 1995.
 
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128/144-MBit Direct RDRAM Data Sheet, Rambus Inc., May 1999.
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Collaborative Colleagues:
G. Chen: colleagues
M. Kandemir: colleagues
H. Saputra: colleagues
M. J. Irwin: colleagues