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ABSTRACT

New timing models have been developed and implemented in the switch-level timing simulator BRASIL which are able to give fairly accurate signal waveforms. This enables the detection of faulty aspect ratios, dynamic hazards and races and timing faults caused by clock skew in NMOS and CMOS circuits. In contrast to most existing switch-level timing simulators the algorithm is not restricted to tree structures of the active subnetworks.

REFERENCES

• 1: R. E. Bryant: "A Switch-Level Model and Simulator for MOS Digital Systems", IEEE Trans. Computers, Vol. C-33, No. 2, Feb. 1984, pp. 160--177.
• 2: R. E. Bryant: "A Survey of Switch-Level Algorithms", IEEE Design & Test of Comp. Vol. 4 No. 4, Aug. 1987, pp 26--40.
• 3: J. P. Hayes: "An Introduction to Switch-Level Modeling", IEEE Design & Test of Comp. Vol. 4 No. 4, Aug. 1987, pp 18--25.
• 4: J. K. Ousterhout: "A Switch-Level Timing Verifier for Digital MOS VLSI", IEEE Trans. CAD of Integrated Circuits and Systems, Vol. CAD-4, No. 3, July 1985, pp. 336--349.
• 5: D. J. Pilling, J. G. Skalnik: "A Circuit Model for Predicting Transient Delays in LSI Logic Systems", Proc. 6th Asilomar Conf. on Circuits and Systems, 1972, pp. 424--428.
• 6: Charles A. Zukowski, The bounding approach to VLSI circuit simulation, Kluwer, B.V., Deventer, The Netherlands, 1986