| A new approach to pipeline optimisation |
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European Design Automation Conference
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Proceedings of the conference on European design automation
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Glasgow, Scotland
SESSION: Scheduling and allocation I
table of contents
Pages: 83 - 88
Year of Publication: 1990
ISBN:0-8186-2024-2
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IEEE Computer Society Press
Los Alamitos, CA, USA
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Downloads (6 Weeks): 3, Downloads (12 Months): 8, Citation Count: 9
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ABSTRACT
This paper presents a new algorithm for the generation of pipelined designs developed for use in an interactive behavioural synthesis system. Our technique uses a novel iterative optimisation algorithm that allows the user to trade-off interactive response time with solution quality. Two examples are given to demonstrate the effectiveness of our approach. These provide comparisons with (i) an expert designer and (ii) recently published algorithms for pipeline synthesis.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Park, N., Parker A. C., "Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications", IEEE Transactions on CAD Vol.7 No.3, March 1988.
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Paulin, P. G., Knight, J. P., "Force-Directed Scheduling For the Behavioral Synthesis of ASIC's", IEEE Transactions on CAD, Vol. 8, No. 6, June 1989.
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G. Goossens , J. Vandewlle , H. De Man, Loop optimization in register-transfer scheduling for DSP-systems, Proceedings of the 26th ACM/IEEE conference on Design automation, p.826-831, June 25-28, 1989, Las Vegas, Nevada, United States
[doi> 10.1145/74382.74384]
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Mallon, D. J., Denyer, P. B., "Behavioural Synthesis: an interactive approach", IEE Colloquium on "Silicon Compilation", 24th May 1989.
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Mallon, D. J., Denyer, P. B., "SAGE: a system for rapid VLSI design", IEE Colloquium on "New Directions in VLSI Design", 27th November 1989.
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Michael C. McFarland , Alice C. Parker , Raul Camposano, Tutorial on high-level synthesis, Proceedings of the 25th ACM/IEEE conference on Design automation, p.330-336, June 12-15, 1988, Atlantic City, New Jersey, United States
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CITED BY 9
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Cheng-Tsung Hwang , Yu-Chin Hsu , Youn-Long Lin, Scheduling for functional pipelining and loop winding, Proceedings of the 28th conference on ACM/IEEE design automation, p.764-769, June 17-22, 1991, San Francisco, California, United States
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Tsing-Fa Lee , Allen C.-H. Wu , Daniel D. Gajski , Youn-Long Lin, An effective methodology for functional pipelining, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.230-233, November 1992, Santa Clara, California, United States
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P. E. R. Lippens , J. L. van Meerbergen , A. van der Werf , W. F. J. Verhaegh , B. T. McSweeney , J. O. Huisken , O. P. McArdle, PHIDEO: a silicon compiler for high speed algorithms, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
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