Automatic exploration of VLIW processor architectures from a designer's experience based specification

ABSTRACT

This paper presents a new synthesis approach for dedicated systems. The aim of our synthesis scheme is to achieve an automatic exploration of VLIW processor architectures from a pure C description of the input system. The innovation consists in the fact that unit allocation must manage the fact that a function may be realized either by dedicated functional units or by a set of lower-level efficiently controlled functional units. For example, execution of a square root function can be accomplished by two ways: either by a dedicated functional unit or by an oriented software implementation of Newton's iterations. The aim is to find the best global trade-off between all the candidate architectures. In order to illustrate this synthesis scheme, we give an example issued from a sonar application.

REFERENCES

• 1: Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
• 2: AUGUIN M., BOERI F., CARRIERE C., MENEZ G. Synthesis of dedicated SIMD processors. Proceedings Application Specific Array Processors. Venise, October 25--27, 1993.
• 3: Mauricio Breternitz, Jr. , John Paul Shen, Architecture synthesis of high-performance application-specific processors, Proceedings of the 27th ACM/IEEE conference on Design automation, p.542-548, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123398]
• 4: BUCK J., HAS., LEE E. A., MESSERSCHMITT D. G. Ptolemy: a mixed paradigm simulation/prototyping platform. Proceedings of Speech Tech. New York, April 23--25, 1991.
• 5: CARRIERE C., AUGUIN M., BOERI F., MENEZ G. A comparison study of minimization methods of unit interconnection in VLIW processors. Proceedings EUROMICRO-92, pages 595--602. Paris, september 14--17, 1992.
• 6: CATTHOOR F. Microcoded processor architectures and synthesis methodology for real time signal processing. Proceedings Algorithms and Parallel Architectures, pages 403--429. Pont-a-Mousson, France, june 10--16, 1990.
• 7: C. Eisenbeis, Optimization of horizontal microcode generation for loop structures, Proceedings of the 2nd international conference on Supercomputing, p.453-465, June 1988, St. Malo, France [doi>10.1145/55364.55408]
• 8: Rolf Ernst , Jorg Henkel , Thomas Benner, Hardware-Software Cosynthesis for Microcontrollers, IEEE Design & Test, v.10 n.4, p.64-75, October 1993 [doi>10.1109/54.245964]
• 9: Guang R. Gao , Yue-Bong Wong , Qi Ning, A timed Petri-net model for fine-grain loop scheduling, Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, p.204-218, June 24-28, 1991, Toronto, Ontario, Canada
• 10: Rajesh K. Gupta , Giovanni De Micheli, Hardware-Software Cosynthesis for Digital Systems, IEEE Design & Test, v.10 n.3, p.29-41, July 1993 [doi>10.1109/54.232470]
• 11: HILFINGER P. N. Silage a high level language and silicon compiler for signal processing. IEEE Conference on Custom Integrated Circuits, pages 213--216. Portland, may, 1985.
• 12: HOLMER B. K., PANGRLE B. M. Hardware-software-codesign-using-automated-instruction-set-design. Proceedings Int. Workshop on Hardware-Software Co-Design. Cambridge, Mass., October 7--8, 1993.
• 13: M. Lam, Software pipelining: an effective scheduling technique for VLIW machines, Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation, p.318-328, June 20-24, 1988, Atlanta, Georgia, United States
• 14: G. Menez , M. Auguin , F. Boéri , C. Carrière, A partitioning algorithm for system-level synthesis, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.482-487, November 1992, Santa Clara, California, United States
• 15: Soo-Mook Moon , Kemal Ebcioglu , Ashok K. Agrawala, Selective Scheduling Framework for Speculative Operations in VLIW and Superscalar Processors, Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, p.229-242, January 20-22, 1993
• 16: STONE H. S. Parallel processing with the perfect shuffle. IEEE Transactions on Computers. C-20153-161, Feb., 1971.
• 17: AUGUIN M., BOERI F., CARRIERE C., MENEZ G. Incremental synthesis of application domain specific processors. Proceedings ICASSP-93, pages 1425--1428. april 27--30, 1993.
• 18: Jiang Wang , Christine Eisenbeis, Decomposed Software Pipelining: A New Approach to Exploit Instruction Level Parallelism for Loop Programs, Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, p.3-14, January 20-22, 1993
• 19: WOLF W., MARTINEZ J. C. C Program Performance Estimation for Embedded Systems Architecture Sizing. Proceedings Int. Workshop on Hardware-Software Co-Design. Cambridge, Mass., October 7--8, 1993.
• 20: Nam S. Woo , Alfred E. Dunlop , Wayne Wolf, Codesign from Cospecification, Computer, v.27 n.1, p.42-47, January 1994 [doi>10.1109/2.248879]