A multiple bit upset tolerant SRAM memory

ABSTRACT

SRAMs are used nowadays in almost every electronic product. However, as technology shrinks transistor sizes, single and multiple bit upsets only observable in space applications previously are now reported at ground level. This article presents a high level technique to protect SRAM memories against multiple upsets based on correcting codes. The proposed technique combines Reed Solomon code and Hamming code to assure reliability in presence of multiple bit flips with reduced area and performance penalties. Multiple upsets were randomly injected in various combinations of memory cells to evaluate the robustness of the method. The experiment was emulated in a Virtex FPGA platform. Results show that 100% of the injected double faults and a large amount of multiple faults were corrected by the method.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.4 Reliability, Testing, and Fault-Tolerance**

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.3 Reliability and Testing**

  E. Data
  E.4 CODING AND INFORMATION THEORY
      Subjects: Error control codes

General Terms:
Design, Reliability

Keywords:
Fault tolerant memory, Hamming and Reed-Solomon codes, fault injection, high-level protection technique, protection against radiation