Branch prediction on demand: an energy-efficient solution

ABSTRACT

High-end processors typically incorporate complex branch predictors consisting of many large structures that together consume a notable fraction of total chip power (more than 10% in some cases). Depending on the applications, some of these resources may remain underused for long periods of time. We propose a methodology to reduce the energy consumption of the branch predictor by characterizing prediction demand using profiling and dynamically adjusting predictor resources accordingly. Specifically, we disable components of the hybrid direction predictor and resize the branch target buffer. Detailed simulations show that this approach reduces the energy consumption in the branch predictor by an average of 72% and up to 89% with virtually no impact on prediction accuracy and performance.

REFERENCES

• 1: D. Albonesi. Selective Cache Ways: On-Demand Cache Resource Allocation. Journal of Instruction-Level Parallelism, 2, 2000.
• 2: R. Iris Bahar , Srilatha Manne, Power and energy reduction via pipeline balancing, Proceedings of the 28th annual international symposium on Computer architecture, p.218-229, June 30-July 04, 2001, Göteborg, Sweden
• 3: Rajeev Balasubramonian , David Albonesi , Alper Buyuktosunoglu , Sandhya Dwarkadas, Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.245-257, December 2000, Monterey, California, United States [doi>10.1145/360128.360153]
• 4: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 5: Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
• 6: Daniele Folegnani , Antonio González, Energy-effective issue logic, Proceedings of the 28th annual international symposium on Computer architecture, p.230-239, June 30-July 04, 2001, Göteborg, Sweden
• 7: Applying Decay Strategies to Branch Predictors for Leakage Energy Savings, Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02), p.442, September 16-18, 2002
• 8: Michael C. Huang , Jose Renau , Josep Torrellas, Positional adaptation of processors: application to energy reduction, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
• 9: V. Krishnan , J. Torrellas, An Direct-Execution Framework for Fast and Accurate Simulation of Superscalar Processors, Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, p.286, October 12-18, 1998
• 10: Srilatha Manne , Artur Klauser , Dirk Grunwald, Pipeline gating: speculation control for energy reduction, Proceedings of the 25th annual international symposium on Computer architecture, p.132-141, June 27-July 02, 1998, Barcelona, Spain
• 11: Dharmesh Parikh , Kevin Skadron , Yan Zhang , Marco Barcella , Mircea R. Stan, Power Issues Related to Branch Prediction, Proceedings of the 8th International Symposium on High-Performance Computer Architecture, p.233, February 02-06, 2002
• 12: N. Jouppi S. Wilton. CACTI: an Enhanced Cache Access and Cycle Time Model. IEEE Journal of Solid-State Circuits, 31(5):677--688, May 1996.
• 13: André Seznec , Stephen Felix , Venkata Krishnan , Yiannakis Sazeides, Design tradeoffs for the Alpha EV8 conditional branch predictor, Proceedings of the 29th annual international symposium on Computer architecture, p.295, May 25-29, 2002, Anchorage, Alaska
• 14: A. Seznec and P. Michaud. De-aliased Hybrid Branch Predictors. Technical Report No. 3618, Institut National de Recherche en Informatique et en Automatique (INRIA), February 1999.
• 15: Se-Hyun Yang , Babak Falsafi , Michael D. Powell , Kaushik Roy , T. N. Vijaykumar, An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches, Proceedings of the 7th International Symposium on High-Performance Computer Architecture, p.147, January 20-24, 2001
• 16: Kenneth C. Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE Micro, v.16 n.2, p.28-40, April 1996 [doi>10.1109/40.491460]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Adaptable architectures

General Terms:
Design, Experimentation, Performance

Keywords:
adaptive, branch prediction, profiling