Checkpointing alternatives for high performance, power-aware processors

ABSTRACT

High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes unattractive in terms of resource and power requirements for future generation processors. We propose out-of-order checkpoint release and checkpoint prediction, two alternatives that require significantly less resources and power while maintaining high-performance. We demonstrate their utility at the register alias table (RAT). Our methods reduce the number of RAT checkpoints to 1/3 (from 48 down to 16) for an aggressive, 8-way superscalar processor with a 256-entry instruction window. Using a 0.18um process model we estimate that RAT power is reduced by 24%.

REFERENCES

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

General Terms:
Algorithms, Design, Experimentation, Performance

Keywords:
checkpointing, out-of-order execution, power density, power-aware, renaming