Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning

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Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2003 international symposium on Low power electronics and design table of contents

Seoul, Korea

SESSION: Energy efficient microarchitectural techniques table of contents

Pages: 306 - 311

Year of Publication: 2003

ISBN:1-58113-682-X

Authors

Hsien-Hsin S. Lee	Georgia Institute of Technology, Atlanta, GAGeorgia Institute of Technology, Atlanta, GA
Chinnakrishnan S. Ballapuram	Georgia Institute of Technology, Atlanta, GA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 24, Citation Count: 9

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ABSTRACT

The memory subsystem, including address translations and cache accesses, consumes a major portion of the overall energy on a processor. In this paper, we address the memory energy issues by using a streamlined architectural partitioning technique that effectively reduces energy consumption in the memory subsystem without compromising performance. It is achieved by decoupling the d-TLB lookups and the data cache accesses, based on the semantic regions defined by programming languages and software convention, into discrete reference substreams --- stack, global static, and heap. Their unique access behaviors and locality characteristics are analyzed and exploited for power reduction. Our results show that an average of 35% energy can be reduced in the d-TLB and the data cache. Furthermore, an average of 46% energy can be saved by selectively multi-porting the semantic-aware d-TLBs and data caches against their monolithic counterparts.

REFERENCES

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	1	David H. Albonesi, Selective cache ways: on-demand cache resource allocation, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.248-259, November 16-18, 1999, Haifa, Israel
	2	Raksit Ashok , Saurabh Chheda , Csaba Andras Moritz, Cool-Mem: combining statically speculative memory accessing with selective address translation for energy efficiency, Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, October 05-09, 2002, San Jose, California
	3	T. M. Austin. Simplescalar 4.0 Release Note. http://www.simplescalar.com/.
	4	A. D. Berenbaum, D. R. Ditzel, and H. R. McLellan. An Introduction to the CRISP Architecture. In Proceedings of the Spring COMPCON, 1987.
	5	R. P. Blake. Exploring a Stack Architecture. IEEE Computer, May 1977.
	6	David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
	7	J. Bradley Chen , Anita Borg , Norman P. Jouppi, A simulation based study of TLB performance, Proceedings of the 19th annual international symposium on Computer architecture, p.114-123, May 19-21, 1992, Queensland, Australia
	8	Sangyeun Cho , Pen-Chung Yew , Gyungho Lee, Decoupling local variable accesses in a wide-issue superscalar processor, Proceedings of the 26th annual international symposium on Computer architecture, p.100-110, May 01-04, 1999, Atlanta, Georgia, United States
	9	J.-H. Choi, J.-H. Lee, S.-W. Jeong, S.-D. Kim, and C. Weems. A Low power TLB structure for Embedded Systems. IEEE Computer TCCA Letter, January 2002.
	10	Jamison Collins , Suleyman Sair , Brad Calder , Dean M. Tullsen, Pointer cache assisted prefetching, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	11	Robert Cooksey , Stephan Jourdan , Dirk Grunwald, A stateless, content-directed data prefetching mechanism, Proceedings of the 10th international conference on Architectural support for programming languages and operating systems, October 05-09, 2002, San Jose, California
	12	Kanad Ghose , Milind B. Kamble, Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation, Proceedings of the 1999 international symposium on Low power electronics and design, p.70-75, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313860]
	13	M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brown. MiBench: A Free, Commercially Representative Embedded Benchmark Suite. In IEEE 4th Workshop on Workload Characterization, 2001.
	14	Michael Huang , Jose Renau , Seung-Moon Yoo , Josep Torrellas, L1 data cache decomposition for energy efficiency, Proceedings of the 2001 international symposium on Low power electronics and design, p.10-15, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383086]
	15	N. Jouppi. CACTI 3.0. http://research.compaq.com/wrl /people/jouppi/CACTI.html, 1999.
	16	Toni Juan , Tomas Lang , Juan J. Navarro, Reducing TLB power requirements, Proceedings of the 1997 international symposium on Low power electronics and design, p.196-201, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263332]
	17	I. Kadayif , A. Sivasubramaniam , M. Kandemir , G. Kandiraju , G. Chen, Generating physical addresses directly for saving instruction TLB energy, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	18	Johnson Kin , Munish Gupta , William H. Mangione-Smith, Filtering Memory References to Increase Energy Efficiency, IEEE Transactions on Computers, v.49 n.1, p.1-15, January 2000 [doi>10.1109/12.822560]
	19	H.-H. S. Lee, J. B. Fryman, A. U. Diril, and Y. S. Dhillon. The Elusive Metric for Low-Power Architecture Research. In Workshop on Complexity-Effective Design in conjunction with ISCA-30, 2003.
	20	Hsien-Hsin S. Lee , Gary S. Tyson, Region-based caching: an energy-delay efficient memory architecture for embedded processors, Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems, p.120-127, November 17-19, 2000, San Jose, California, United States [doi>10.1145/354880.354898]
	21	James Montanaro , Richard T. Witek , Krishna Anne , Andrew J. Black , Elizabeth M. Cooper , Daniel W. Dobberpuhl , Paul M. Donahue , Jim Eno , Gregory W. Hoeppner , David Kruckemyer , Thomas H. Lee , Peter C. M. Lin , Liam Madden , Daniel Murray , Mark H. Pearce , Sribalan Santhanam , Kathryn J. Snyder , Ray Stephany , Stephen C. Thierauf, A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor, Digital Technical Journal, v.9 n.1, p.49-62, 1997
	22	Ching-Long Su , Alvin M. Despain, Cache design trade-offs for power and performance optimization: a case study, Proceedings of the 1995 international symposium on Low power design, p.63-68, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224093]

CITED BY 9

	Dongrui Fan , Zhimin Tang , Hailin Huang , Guang R. Gao, An energy efficient TLB design methodology, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	M. Kandemir , I. Kadayif , G. Chen, Compiler-directed code restructuring for reducing data TLB energy, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
	I. Kadayif , A. Sivasubramaniam , M. Kandemir , G. Kandiraju , G. Chen, Optimizing instruction TLB energy using software and hardware techniques, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.229-257, April 2005
	Chinnakrishnan S. Ballapuram , Hsien-Hsin S. Lee , Milos Prvulovic, Synonymous address compaction for energy reduction in data TLB, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Chinnakrishnan Ballapuram , Kiran Puttaswamy , Gabriel H. Loh , Hsien-Hsin S. Lee, Entropy-based low power data TLB design, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea
	Xiangrong Zhou , Peter Petrov, Direct address translation for virtual memory in energy-efficient embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.8 n.1, p.1-31, December 2008
	Mingming Zhang , Xiaotao Chang , Ge Zhang, Reducing cache energy consumption by tag encoding in embedded processors, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Olga Golubeva , Mirko Loghi , Enrico Macii , Massimo Poncino, Locality-driven architectural cache sub-banking for leakage energy reduction, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Chinnakrishnan S. Ballapuram , Ahmad Sharif , Hsien-Hsin S. Lee, Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors, ACM SIGPLAN Notices, v.43 n.3, March 2008