Voltage scheduling under unpredictabilities

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Voltage scheduling under unpredictabilities: a risk management paradigm

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2003 international symposium on Low power electronics and design table of contents

Seoul, Korea

SESSION: System estimation and voltage scheduling table of contents

Pages: 302 - 305

Year of Publication: 2003

ISBN:1-58113-682-X

Authors

Azadeh Davoodi	University of Maryland, College Park, MD
Ankur Srivastava	University of Maryland, College Park, MD

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 5, Citation Count: 5

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ABSTRACT

This paper addresses the problem of voltage scheduling in unpredictable situations. The voltage scheduling problem assigns voltages to operations such that the power is minimized under a clock cycle constraint. In presence of unpredictabilities meeting the clock constraint cannot be guaranteed. This paper proposes a novel risk management based technique to solve this problem. The risk management paradigm assigns a quantified value to the amount of risk the designer is willing to take on the clock cycle constraint. The algorithm then assigns voltages in order to meet the expected value of clock cycle constraint while keeping the maximum delay within the specified "risk" and minimizing the power.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Ankur Srivastava , Majid Sarrafzadeh, Predictability: definition, ananlysis and optimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.118-121, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774589]
	2	Salil Raje , Majid Sarrafzadeh, Variable voltage scheduling, Proceedings of the 1995 international symposium on Low power design, p.9-14, April 23-26, 1995, Dana Point, California, United States [doi>10.1145/224081.224084]
	3	A.P. Chandrakasan, S. Sheng and R.W. Brodersen. "Low Power CMOS Digital Design". In IEEE Journal of Solid State Circuits, pages 472--484, April 1992.
	4	Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	5	Jui-Ming Chang , Massoud Pedram, Energy minimization using multiple supply voltages, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.436-443, Dec. 1997 [doi>10.1109/92.645070]

CITED BY 5

	Azadeh Davoodi , Vishal Khandelwal , Ankur Srivastava, Empirical models for net-length probability distribution and applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1066-1075, October 2004
	Azadeh Davoodi , Ankur Srivastava, Simultaneous floorplanning and resource binding: a probabilistic approach, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Yan Lin , Lei He, Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays, February 18-20, 2007, Monterey, California, USA
	A. Davoodi , V. Khandelwal , A. Srivastava, Variability inspired implementation selection problem, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.423-427, November 07-11, 2004
	Vishal Khandelwal , Azadeh Davoodi , Akash Nanavati , Ankur Srivastava, A Probabilistic Approach to Buffer Insertion, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.560, November 09-13, 2003