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ABSTRACT

While circuit and package designers have addressed microprocessor inductive noise issues in the past, multi-gigahertz clock frequencies and billion-transistor-level integration are exacerbating the problem, necessitating microarchitectural solutions. The large net on-die decoupling capacitance used to address this noise throughout the chip consumes substantial area and can cause a large leakage current. This paper proposes microarchitectural techniques to reduce high-frequency current variability, reducing the need for decoupling capacitors. We observe that we can control inductive noise by reducing current variability either in space (i.e., variability in usage of circuit blocks) or in time (i.e., variability within a circuit block across clock cycles). We propose pipeline muffling, a novel technique to reduce changes in the number of resources being utilized by controlling instruction issue, trading off some energy and performance to control di/dt in space. We also extend a previous technique, which incurs performance and energy degradation, and propose a priori current ramping to allow the current of a resource to ramp up ahead of usage, with virtually no performance loss, and ramp down immediately after usage, with little energy loss. Our techniques guarantee a worst-case bound on the di/dt, which is required to reduce the demand for decoupling capacitors, saving area and reducing leakage.

REFERENCES

• 1: W. Becker, H. Smith, T. McNamara, P. Muench, J. Eckhardt, M. McAllister, and G. Katopis. Mid-frequency simultaneous switching noise in computer systems. In 1997 Electronic Components and Technology Conference, pages 676--681, 1997.
• 2: Darrell Boggs, Breathing life into a paper tiger (keynote session), Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.5, December 2000, Monterey, California, United States [doi>10.1145/360128.360130]
• 3: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 4: D. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. Technical Report 1342, Computer Sciences Department, University of Wisconsin-Madison, June 1997.
• 5: Yi-Shing Chang , Sandeep K. Gupta , Melvin A. Breuer, Analysis of Ground Bounce in Deep Sub-Micron Circuits, Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), p.110, April 27-May 01, 1997
• 6: Wael El-Essawy , David H. Albonesi , Balaram Sinharoy, A microarchitectural-level step-power analysis tool, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566477]
• 7: IEEE Design & Test Staff, A D&T Roundtable: Power Delivery and Distribution, IEEE Design & Test, v.17 n.4, p.98-102, October 2000
• 8: Dave Ayers, Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation, Proceedings of the 8th International Symposium on High-Performance Computer Architecture, p.7, February 02-06, 2002
• 9: D. J. Herrell and B. Beker. Modeling of power distribution systems for high-performance microprocessors. IEEE Transactions on Advanced Packaging, 22(3):240--248, 1999.
• 10: Russ Joseph , David Brooks , Margaret Martonosi, Control Techniques to Eliminate Voltage Emergencies in High Performance Processors, Proceedings of the 9th International Symposium on High-Performance Computer Architecture, p.79, February 08-12, 2003
• 11: Hai Li , Swarup Bhunia , Yiran Chen , T. N. Vijaykumar , Kaushik Roy, Deterministic Clock Gating for Microprocessor Power Reduction, Proceedings of the 9th International Symposium on High-Performance Computer Architecture, p.113, February 08-12, 2003
• 12: Mondira Deb Pant , Pankaj Pant , D. Scott Wills , Vivek Tiwari, An architectural solution for the inductive noise problem due to clock-gating, Proceedings of the 1999 international symposium on Low power electronics and design, p.255-257, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313938]
• 13: Mondira Deb Pant , Pankaj Pant , Donald Scott Wills, On-chip decoupling capacitor optimization using architectural level prediction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.319-326, June 2002 [doi>10.1109/TVLSI.2002.1043335]
• 14: Michael D. Powell , T. N. Vijaykumar, Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage, Proceedings of the 30th annual international symposium on Computer architecture, June 09-11, 2003, San Diego, California
• 15: A. Tang, N. Chang, S. Lin, W. Xie, S. Nakagawa, and L. He. Ramp up/down floating point unit to reduce inductive noise. In Lecture Notes in Computer Science, volume 2008, pages 291--321, 2001.
• 16: Han-Saem Yun , Jihong Kim, Power-aware modulo scheduling for high-performance VLIW processors, Proceedings of the 2001 international symposium on Low power electronics and design, p.40-45, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383091]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.0 General

General Terms:
Reliability

Keywords:
a priori current ramping, decoupling capacitors, inductive noise, leakage, pipeline muffling