Microarchitecture level power and thermal simulation considering temperature dependent leakage model

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Microarchitecture level power and thermal simulation considering temperature dependent leakage model

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2003 international symposium on Low power electronics and design table of contents

Seoul, Korea

SESSION: Temperature and power aware architectures table of contents

Pages: 211 - 216

Year of Publication: 2003

ISBN:1-58113-682-X

Authors

Weiping Liao	University of California at Los Angeles, Los Angeles, CA
Fei Li	University of California at Los Angeles, Los Angeles, CA
Lei He	University of California at Los Angeles, Los Angeles, CA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 39, Citation Count: 11

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ABSTRACT

In this paper, we present power models with clock and temperature scaling, and develop the first of its type coupled thermal and power simulation with temperature-dependent leakage power model at micro-architecture level. We show that leakage energy and total energy can be different by up to 2.5X and 2X for temperatures between 90°C and 130°C, respectively. Given such big energy variations, no power model at microarchitecture level is accurate without considering temperature dependent leakage models.

REFERENCES

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CITED BY 11

	Mahesh Mamidipaka , Kamal Khouri , Nikil Dutt , Magdy Abadir, Analytical models for leakage power estimation of memory array structures, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
	Rajarshi Mukherjee , Seda Ogrenci Memik , Gokhan Memik, Temperature-aware resource allocation and binding in high-level synthesis, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Rajarshi Mukherjee , Seda Ogrenci Memik , Gokhan Memik, Peak temperature control and leakage reduction during binding in high level synthesis, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	G. Paci , P. Marchal , F. Poletti , L. Benini, Exploring "temperature-aware" design in low-power MPSoCs, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Domenik Helms , Günter Ehmen , Wolfgang Nebel, Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	Madhu Mutyam , Feihui Li , Vijaykrishnan Narayanan , Mahmut Kandemir , Mary Jane Irwin, Compiler-directed thermal management for VLIW functional units, ACM SIGPLAN Notices, v.41 n.7, July 2006
	Michael Healy , Mario Vittes , Mongkol Ekpanyapong , Chinnakrishnan Ballapuram , Sung Kyu Lim , Hsien-Hsin S. Lee , Gabriel H. Loh, Microarchitectural floorplanning under performance and thermal tradeoff, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Jonathan A. Winter , David H. Albonesi, Addressing thermal nonuniformity in SMT workloads, ACM Transactions on Architecture and Code Optimization (TACO), v.5 n.1, p.1-28, May 2008
	Sungpack Hong , Sungjoo Yoo , Byeong Bin , Kyu-Myung Choi , Soo-Kwan Eo , Taehwan Kim, Dynamic voltage scaling of supply and body bias exploiting software runtime distribution, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Rajarshi Mukherjee , Seda Ogrenci Memik, An integrated approach to thermal management in high-level synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.11, p.1165-1174, November 2006
	Kanupriya Gulati , Sunil P. Khatri , Peng Li, Closed-loop modeling of power and temperature profiles of FPGAs, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, February 22-24, 2009, Monterey, California, USA