Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation

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Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2003 international symposium on Low power electronics and design table of contents

Seoul, Korea

SESSION: Power estimation and design for scaled technologies table of contents

Pages: 172 - 175

Year of Publication: 2003

ISBN:1-58113-682-X

Authors

Saibal Mukhopadhyay	Purdue University, West Lafayette, IN
Kaushik Roy	Purdue University, West Lafayette, IN

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 89, Citation Count: 27

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ABSTRACT

In this paper we have developed analytical models to estimate the mean and the standard deviation in the gate, the subthreshold, the reverse biased source/drain junction band-to-band-tunneling (BTBT) and the total leakage in scaled CMOS devices considering variation in process parameters like device geometry, doping profile, flat-band voltage and supply voltage. We have verified the model using Monte Carlo simulation using an NMOS device of 50nm effective length and analyzed the results to enumerate the effect of different process parameters on the individual components and the total leakage.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Rajeev R. Rao , David Blaauw , Dennis Sylvester , Anirudh Devgan, Modeling and Analysis of Parametric Yield under Power and Performance Constraints, IEEE Design & Test, v.22 n.4, p.376-385, July 2005
	Rajeev R. Rao , Anirudh Devgan , David Blaauw , Dennis Sylvester, Parametric yield estimation considering leakage variability, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Vishal Khandelwal , Ankur Srivastava, Active mode leakage reduction using fine-grained forward body biasing strategy, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Songqing Zhang , Vineet Wason , Kaustav Banerjee, A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Jeong-Taek Kong, CAD for nanometer silicon design challenges and success, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.11, p.1132-1147, November 2004
	Hongliang Chang , Sachin S. Sapatnekar, Full-chip analysis of leakage power under process variations, including spatial correlations, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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