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New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 2003 international symposium on Low power electronics and design table of contents
Seoul, Korea
SESSION: Power estimation and design for scaled technologies table of contents
Pages: 168 - 171  
Year of Publication: 2003
ISBN:1-58113-682-X
Authors
Koushik K. Das  University of Michigan, Ann Arbor, MI
Rajiv V. Joshi  IBM TJ Watson Research Center Yorktown Heights, NY
Ching-Te Chuang  IBM TJ Watson Research Center Yorktown Heights, NY
Peter W. Cook  IBM TJ Watson Research Center Yorktown Heights, NY
Richard B. Brown  University of Michigan, Ann Arbor, MI
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
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ABSTRACT

This paper proposes new SOI circuit strategies for simultaneous reduction of standby gate and sub-threshold leakages. Various enhanced MTCMOS design alternatives are analyzed. A new method for assigning the VTH and sizes of header and footer transistors is proposed, and stacking of headers/footers is analyzed. The optimum stacking height and tapering/sizing ratio under various design constraints are determined. Our strategies reduce MTCMOS standby leakage further by as much as 20X and reduce virtual supply noise by 15%.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
F. Hamzaoglu and M. R. Stan, ISLPED 2002, pp. 60--63.
 
2
S. Mutoh, et. al., IEEE JSSC, August 1995, pp. 847--854.
3
Siva Narendra , Vivek De , Dimitri Antoniadis , Anantha Chandrakasan , Shekhar Borkar, Scaling of stack effect and its application for leakage reduction, Proceedings of the 2001 international symposium on Low power electronics and design, p.195-200, August 2001, Huntington Beach, California, United States  [doi>10.1145/383082.383132]
 
4
Yibin Ye, et. al., 1998 Symp. of VLSI Circuits, pp. 40--41.
 
5
K. K. Das and R. B. Brown, 2002 SOI Conf., pp. 88--90.
 
6
T. Inukai, et. al., 2000 IEEE CICC, pp. 409--412.
 
7
K.-Y. Toh, et. al., JSSC, August 1988, pp. 950--958.
 
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K. M. Cao, et. al., 2000 IEDM Tech. Dig., pp. 815--818.
9
Zhanping Chen , Mark Johnson , Liqiong Wei , Kaushik Roy, Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks, Proceedings of the 1998 international symposium on Low power electronics and design, p.239-244, August 10-12, 1998, Monterey, California, United States  [doi>10.1145/280756.280917]

CITED BY
Rahul Rao , Kanak Agarwal , Dennis Sylvester , Richard Brown , Kevin Nowka , Sani Nassif, Approaches to run-time and standby mode leakage reduction in global buses, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)


General Terms:
Design, Performance, Theory


Keywords:
SOI, VLSI, circuits, high-performance, leakage-power

Collaborative Colleagues:
Koushik K. Das: colleagues
Rajiv V. Joshi: colleagues
Ching-Te Chuang: colleagues
Peter W. Cook: colleagues
Richard B. Brown: colleagues

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