Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization

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Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2003 international symposium on Low power electronics and design table of contents

Seoul, Korea

SESSION: Advances in low power synthesis table of contents

Pages: 158 - 163

Year of Publication: 2003

ISBN:1-58113-682-X

Authors

David Nguyen	University of California at Berkeley, CA
Abhijit Davare	University of California at Berkeley, CA
Michael Orshansky	University of California at Berkeley, CA
David Chinnery	University of California at Berkeley, CA
Brandon Thompson	University of California at Berkeley, CA
Kurt Keutzer	University of California at Berkeley, CA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 62, Citation Count: 23

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ABSTRACT

We describe an optimization strategy for minimizing total power consumption using dual threshold voltage (Vth) technology. Significant power savings are possible by simultaneous assignment of Vth with gate sizing. We propose an efficient algorithm based on linear programming that jointly performs Vth assignment and gate sizing to minimize total power under delay constraints. First, linear programming assigns the optimal amounts of slack to gates based on power-delay sensitivity. Then, an optimal gate configuration, in terms of Vth and transistor sizes, is selected by an exhaustive local search. Benchmark results for the algorithm show 32% reduction in power consumption on average, compared to sizing only power minimization. There is up to a 57% reduction for some circuits. The flow can be extended to dual supply voltage libraries to yield further power savings.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 23

	Mongkol Ekpanyapong , Sung Kyu Lim, Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Murari Mani , Anirudh Devgan , Michael Orshansky, An efficient algorithm for statistical minimization of total power under timing yield constraints, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	W. Hung , Y. Xie , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , Y. Tsai, Total power optimization through simultaneously multiple-v_DD multiple-v_TH assignment and device sizing with stack forcing, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Ashish Srivastava , Dennis Sylvester , David Blaauw, Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Sarvesh H. Kulkarni , Dennis Sylvester, Power distribution techniques for dual VDD circuits, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Sarvesh H. Kulkarni , Dennis Sylvester, High performance level conversion for dual VDD design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.9, p.926-936, September 2004
	D. G. Chinnery , K. Keutzer, Linear programming for sizing, V_th and V_dd assignment, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Feng Gao , John P. Hayes, Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Nader Ben Amor , Yannick Le Moullec , Jean Philippe Diguet , Jean Luc Philippe , Mohamed Abid, Design of a multimedia processor based on metrics computation, Advances in Engineering Software, v.36 n.7, p.448-458, July 2005
	Yu-Hui Huang , Po-Yuan Chen , TingTing Hwang, Switching-activity driven gate sizing and Vth assignment for low power design, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Hsinwei Chou , Yu-Hao Wang , Charlie Chung-Ping Chen, Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Sanjukta Bhanja , Karthikeyan Lingasubramanian , N. Ranganathan, A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.773-796, July 2006
	Min Ni , Seda Ogrenci Memik, Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	N. Ranganathan , U. Gupta , V. Mahalingam, Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Zuying Luo, General transistor-level methodology on VLSI low-power design, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Jeegar Tilak Shah , Marius Evers , Jeff Trull , Alper Halbutogullari, Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	Stephen P. Boyd , Seung-Jean Kim , Dinesh D. Patil , Mark A. Horowitz, Digital Circuit Optimization via Geometric Programming, Operations Research, v.53 n.6, p.899-932, November-December 2005
	Min Ni , Seda Ogrenci Memik, Thermal-induced leakage power optimization by redundant resource allocation, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	S. Shah , A. Srivastava , D. Sharma , D. Sylvester , D. Blaauw , V. Zolotov, Discrete Vt assignment and gate sizing using a self-snapping continuous formulation, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.705-712, November 06-10, 2005, San Jose, CA
	Sarvesh Bhardwaj , Sarma Vrudhula, Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.713-718, November 06-10, 2005, San Jose, CA
	Yu-Cheng Lin , Hsin-Hsiung Huang , Cheng-Chiang Lin , Tsai-Ming Hsieh, Optimal voltage assignment approach for low power using ILP, WSEAS Transactions on Circuits and Systems, v.7 n.7, p.728-737, July 2008
	Yifang Liu , Jiang Hu, A new algorithm for simultaneous gate sizing and threshold voltage assignment, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA
	Yu-Cheng Lin , Cheng-Chiang Lin , Hsin-Hsiung Huang , Tsai-Ming Hsieh, Optimal dual voltage assignment algorithm for low power under timing-constraints, Proceedings of the 12th WSEAS international conference on Circuits, p.202-205, July 22-24, 2008, Heraklion, Greece