Simultaneous Vt selection and assignment for leakage optimization

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Simultaneous Vt selection and assignment for leakage optimization

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2003 international symposium on Low power electronics and design table of contents

Seoul, Korea

SESSION: Advances in low power synthesis table of contents

Pages: 146 - 151

Year of Publication: 2003

ISBN:1-58113-682-X

Author

Ankur Srivastava

University of Maryland, College Park, MD

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 14, Citation Count: 7

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ABSTRACT

This paper presents a novel approach for leakage optimization through simultanous Vt selection and assignment. Vt selection implies deciding the right value for $V_t$ and assignment implies deciding which gates should be assigned which thresh-hold value. The proposed algorithm is a general mathematical formulation that can be trivially extended to multiple thresh-hold voltages (more than two). Traditional leakage optimization strategies either assume the prespecification of thresh-hold values or are good only for two thresh-holds. The presented formulation is based on linear programming approach under the piecewise linear approximation of delay/leakage vs thresh-hold curves. The algortihm was incorporated in SIS. Experimental results indicate that on some benchmarks having more that two thresh-holds was beneficial for leakage.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 8

	Behnam Amelifard , Farzan Fallah , Massoud Pedram, Low-power fanout optimization using multiple threshold voltage inverters, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Behnam Amelifard , Farzan Fallah , Massoud Pedram, Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Lara D. Oliver , Krishnendu Chakrabarty , Hisham Z. Massoud, An evaluation of the impact of gate oxide tunneling on dual-V_t-based leakage reduction techniques, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Jeegar Tilak Shah , Marius Evers , Jeff Trull , Alper Halbutogullari, Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors, Proceedings of the 2007 international symposium on Physical design, March 18-21, 2007, Austin, Texas, USA
	S. Shah , A. Srivastava , D. Sharma , D. Sylvester , D. Blaauw , V. Zolotov, Discrete Vt assignment and gate sizing using a self-snapping continuous formulation, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.705-712, November 06-10, 2005, San Jose, CA
	Behnam Amelifard , Massoud Pedram , Farzan Fallah, Low-leakage SRAM Design with Dual V_t Transistors, Proceedings of the 7th International Symposium on Quality Electronic Design, p.729-734, March 27-29, 2006
	Behnam Amelifard , Farzan Fallah , Massoud Pedram, Leakage minimization of SRAM cells in a dual-V t and Dual-T ox technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.851-860, July 2008
	Behnam Amelifard , Farzan Fallah , Massoud Pedram, Low-power fanout optimization using multi threshold voltages and multi channel lengths, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.4, p.478-489, April 2009