Low-power high-level synthesis for FPGA architectures

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Low-power high-level synthesis for FPGA architectures

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2003 international symposium on Low power electronics and design table of contents

Seoul, Korea

SESSION: Advances in low power synthesis table of contents

Pages: 134 - 139

Year of Publication: 2003

ISBN:1-58113-682-X

Authors

Deming Chen	University of California, Los Angeles, CA
Jason Cong	University of California, Los Angeles, CA
Yiping Fan	University of California, Los Angeles, CA

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 80, Citation Count: 17

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ABSTRACT

This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estimator closely reflects both dynamic and static power contributed by various FPGA components in 0.1um technology. The power estimation error is 16.2% on average. Second, we present a low power high level synthesis system, named LOPASS, for FPGA designs. It includes two algorithms for power consumption reduction: (i) a simulated annealing engine that carries out resource selection, function unit binding, scheduling, register binding, and data path generation simultaneously to effectively reduce power; (ii) an enhanced weighted bipartite matching algorithm that is able to reduce the total amount of MUX ports by 22.7%. Experimental results show that LOPASS is able to reduce power consumption by 35.8% compared to the results of Synopsys' Behavioral Compiler.

REFERENCES

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CITED BY 17

	Deming Chen , Jason Cong, Register binding and port assignment for multiplexer optimization, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.68-73, January 27-30, 2004, Yokohama, Japan
	Deming Chen , Jason Cong, Delay optimal low-power circuit clustering for FPGAs with dual supply voltages, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	A. Gayasen , Y. Tsai , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , T. Tuan, Reducing leakage energy in FPGAs using region-constrained placement, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Deming Chen , Jason Cong , Junjuan Xu, Optimal module and voltage assignment for low-power, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Somsubhra Mondal , Seda Öǧrenci Memik, Resource sharing in pipelined CDFG synthesis, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Taemin Kim , Xun Liu, Compatibility path based binding algorithm for interconnect reduction in high level synthesis, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Deming Chen , Jason Cong , Yiping Fan , Junjuan Xu, Optimality study of resource binding with multi-Vdds, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Deming Chen , Jason Cong , Junjuan Xu, Optimal simultaneous module and multivoltage assignment for low power, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.2, p.362-386, April 2006
	Jason Cong , Yiping Fan , Wei Jiang, Platform-based resource binding using a distributed register-file microarchitecture, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Deming Chen , Jason Cong , Peichen Pan, FPGA Design Automation: A Survey, Foundations and Trends® in Electronic Design Automation, v.1 n.3, p.139-169, January 2006
	Jason Cong , Wei Jiang, Pattern-based behavior synthesis for FPGA resource reduction, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Rajarshi Mukherjee , Song Liu , Seda Ogrenci Memik , Somsubhra Mondal, A high-level clustering algorithm targeting dual V_dd FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.4, p.1-20, September 2008
	Jason Cong , Junjuan Xu, Simultaneous FU and register binding based on network flow method, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Qiang Wang , Subodh Gupta , Jason H. Anderson, Clock power reduction for virtex-5 FPGAs, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, February 22-24, 2009, Monterey, California, USA
	Taemin Kim , Xun Liu, Better than optimum?: register reduction using idle pipelined functional units, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA
	Jason Cong , Yiping Fan , Junjuan Xu, Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.14 n.3, p.1-31, May 2009
	Ruzica Jevtic , Carlos Carreras , Vukasin Pejovic, Floorplan-based FPGA interconnect power estimation in DSP circuits, Proceedings of the 11th international workshop on System level interconnect prediction, July 26-27, 2009, San Francisco, CA, USA