An MTCMOS design methodology and its application to mobile computing

ABSTRACT

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are used to implement the desired function, the high Vth transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for the Samsung's 0.18?m process, (ii) propose a new special flip-flop which keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a Personal Digital Assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18?m process. The fabricated PDA processor operates at 333MHz, and consumes about 2?W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.

REFERENCES

• 1: S. Mutoh, et al., "A 1V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application", ISSCC, 1996.
• 2: T. Kuroda, et al., "A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable- Threshold Voltage Scheme" ISSCC, 1996.
• 3: S. Shigematsu, S. Mutoh, et al, "A 1-V high-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits", IEEE Journal of Solid-state Circuits, 1997.
• 4: H. Makino, et al., T. Shimizu and T. Arakawa, "An Auto-Backgate-Controlled MT-CMOS Circuit", Symp. on VLSI Circuits Digest of Technical Papers, 1998.
• 5: K. Kumagai, et al., "A Novel Powering-down Scheme for Low Vt CMOS Circuits", Symp. on VLSI Circuits Digest of Technical Papers, 1998.
• 6: Ali Keshavarzi , Siva Narendra , Shekhar Borkar , Charles Hawkins , Kaushik Roy , Vivek De, Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's, Proceedings of the 1999 international symposium on Low power electronics and design, p.252-254, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313937]
• 7: James Kao , Siva Narendra , Anantha Chandrakasan, MTCMOS hierarchical sizing based on mutual exclusive discharge patterns, Proceedings of the 35th annual conference on Design automation, p.495-500, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277180]
• 8: S. Mutoh, et al., "Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs", ASP-DAC, 1999.
• 9: J.T. Kao and A.P. Chandrakasan, "Dual- Threshold Voltage Techniques for Low-Power Digital Circuits", Journal of Solid-State Circuits, 2000.
• 10: K.T. Park, H.S. Won et al., "A New Low -Power Edge-Triggered and Logic-Embedded FF Using Complementary Pass-Transistors Circuit", ITC-CSCC, 2001.
• 11: K.T. Park, H.S. Won et al., "Low-Power Data-Preserving Complementary Pass-Transistor-Based Circuit for Power-Down Circuit Scheme", SSDM, 2001.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design, Experimentation, Measurement, Performance

Keywords:
CCS, CPFF, MTCMOS, leakage current, low power