Efficient techniques for gate leakage estimation

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Efficient techniques for gate leakage estimation

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 2003 international symposium on Low power electronics and design table of contents

Seoul, Korea

SESSION: Leakage estimation table of contents

Pages: 100 - 103

Year of Publication: 2003

ISBN:1-58113-682-X

Authors

Rahul M. Rao	University of Michigan, Ann Arbor, MI
Jeffrey L. Burns	IBM, Austin, TX
Anirudh Devgan	IBM, Austin, TX
Richard B. Brown	University of Michigan, Ann Arbor, MI

Sponsors

ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 38, Citation Count: 6

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ABSTRACT

Gate leakage current is expected to be the dominant leakage component in future technology generations. In this paper, we propose methods for steady-state gate leakage estimation based on state characterization. An efficient technique for pattern-dependent gate leakage estimation is presented. Further, we propose the use of this technique for estimating the average gate leakage of a circuit using pattern-independent probabilistic analysis. Results on a large set of benchmark ISCAS circuits show an accuracy within 5% of SPICE results with 500X to 50000X speed improvement.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	International Technology Roadmap for SemiConductors, http://public.itrs.net/Files/2001ITRS/Home.html.
	2	R. Langevelde, A. Scholten, R. Duffy, F. Cubaynes, M. Knitel and D. Klaassen, "Gate current: Modeling, Extraction and impact on RF performance,"
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	4	C. T. Chuang and R. Puri, "Effects of Gate-to-Body Tunneling Current on Pass-Transistor Based PD/SOI CMOS Circuits," IEEE Intnl. SOI Conf., pp. 121--122, Oct. 2002.
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	6	Fatih Hamzaoglu , Mircea R. Stan, Circuit-level techniques to control gate leakage for sub-100nm CMOS, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566425]
	7	K. Yang, et.al, "Edge Hole Direct Tunneling Leakage in Ultrathin Gate Oxide p-Channel MOSFETs," IEEE Trans. on Electron Devices, vol. 48, no. 12, pp. 2790--2795, Dec. 2001.
	8	Emrah Acar , Anirudh Devgan , Rahul Rao , Ying Liu , Haihua Su , Sani Nassif , Jeffrey Burns, Leakage and leakage sensitivity computation for combinational circuits, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871532]

CITED BY 6

	Andrew B. Kahng , Swamy Muddu , Puneet Sharma, Defocus-aware leakage estimation and control, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Ashesh Rastogi , Wei Chen , Sandip Kundu, On estimating impact of loading effect on leakage current in sub-65nm scaled CMOS circuits based on Newton-Raphson method, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Andrew B. Kahng , Swamy Muddu , Puneet Sharma, Detailed placement for leakage reduction using systematic through-pitch variation, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA
	Paulo F. Butzen , Leomar S. Rosa Jr. , Erasmo J.D. Chiappetta Filho , Dionatan S. Moura , Andre I. Reis , Renato P. Ribas, Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Ashesh Rastogi , Kunal P. Ganeshpure , Alodeep Sanyal , Sandip Kundu, On Composite Leakage Current Maximization, Journal of Electronic Testing: Theory and Applications, v.24 n.4, p.405-420, August 2008
	Kyung Ki Kim , Yong-Bin Kim, Statistical timing and leakage power analysis of PD-SOI digital circuits, Analog Integrated Circuits and Signal Processing, v.60 n.1-2, p.127-136, August 2009