| Estimating influence of data layout optimizations on SDRAM energy consumption |
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International Symposium on Low Power Electronics and Design
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Proceedings of the 2003 international symposium on Low power electronics and design
table of contents
Seoul, Korea
SESSION: Power modeling and optimization for embedded systems
table of contents
Pages: 40 - 43
Year of Publication: 2003
ISBN:1-58113-682-X
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Authors
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H. S. Kim
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The Pennsylvania State University, University Park, PA
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N. Vijaykrishnan
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The Pennsylvania State University, University Park, PA
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M. Kandemir
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The Pennsylvania State University, University Park, PA
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E. Brockmeyer
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IMEC, Kapeldreef 75, Leuven, Belgium
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F. Catthoor
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IMEC, Kapeldreef 75, Leuven, Belgium
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M. J. Irwin
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The Pennsylvania State University, University Park, PA
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Downloads (6 Weeks): 9, Downloads (12 Months): 27, Citation Count: 2
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ABSTRACT
An important problem in extracting maximum benefits from an SDRAM-based architecture is to exploit data locality at the page granularity. Frequent switches between data pages can increase memory latency and have an impact on energy consumption. In this paper, we propose a mathematical formulation, using Presburger arithmetic and Ehrhart polynomials to estimate the number of page breaks statically (i.e., at compile time). The results obtained using video codes indicate that the proposed framework can estimate the number of page breaks with good accuracy.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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