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Estimating influence of data layout optimizations on SDRAM energy consumption
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 2003 international symposium on Low power electronics and design table of contents
Seoul, Korea
SESSION: Power modeling and optimization for embedded systems table of contents
Pages: 40 - 43  
Year of Publication: 2003
ISBN:1-58113-682-X
Authors
H. S. Kim  The Pennsylvania State University, University Park, PA
N. Vijaykrishnan  The Pennsylvania State University, University Park, PA
M. Kandemir  The Pennsylvania State University, University Park, PA
E. Brockmeyer  IMEC, Kapeldreef 75, Leuven, Belgium
F. Catthoor  IMEC, Kapeldreef 75, Leuven, Belgium
M. J. Irwin  The Pennsylvania State University, University Park, PA
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 9,   Downloads (12 Months): 27,   Citation Count: 2
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ABSTRACT

An important problem in extracting maximum benefits from an SDRAM-based architecture is to exploit data locality at the page granularity. Frequent switches between data pages can increase memory latency and have an impact on energy consumption. In this paper, we propose a mathematical formulation, using Presburger arithmetic and Ehrhart polynomials to estimate the number of page breaks statically (i.e., at compile time). The results obtained using video codes indicate that the proposed framework can estimate the number of page breaks with good accuracy.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
The micron system-power calculator. In www.micron.com/products/category.jsp?path=/DRAM/SDRAM&edID=17594.
 
2
The Omega project. In http://www.cs.umd.edu/projects/omega/.
 
3
UTDSP benchmark suite. In http://www.eecg.toronto.edu/ corinna/DSP/infrastructure/UTDSP.html.
 
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A. Khare, P. R. Panda, N. Dutt, and A. Nicolau. High-level synthesis with synchronous and RAMBUS DRAMs. Technical Report 98-28, University of California, Irvine, 1998.
 
9
H. Kim and I.-C. Park. High performance and low-power memory-interface architecture for video processing applications. IEEE Transaction on Circuits and Systems for Video Technology, 11(11):1160--1170, November 2001.
 
10
G. Kreisel and J. L. Krevine. Elements of Mathematical Logic. North-Holland Pub. Co., 1967.
 
11
V. Loechner. Polylib: A library of polyhedral functions. In http://icps.u-strasbg.fr/PolyLib/, 1999.


Collaborative Colleagues:
H. S. Kim: colleagues
N. Vijaykrishnan: colleagues
M. Kandemir: colleagues
E. Brockmeyer: colleagues
F. Catthoor: colleagues
M. J. Irwin: colleagues