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ABSTRACT
MANY PUBLISHED efforts in the field of logical simulation indicate that the programming concept of “compiling and executing” is the most frequently used foundation for the construction of simulation programs. The technique to be described here represents a complete departure from the concept of “compiling and executing”. The basic framework for the simulation method to be presented is simply a close imitation of the structure and operation of a logical network. Applying this concept leads to a realistically operating “general purpose” simulator. The resulting simulation possibilities are—at least with respect to the field of logical simulation—relatively unexplored and unexploited. Simulation in other fields, e.g., the simulation of nerve nets by Reiss1, has preceded the field of logical simulation in taking advantage of the structure and operation of (neural) networks. The first success in applying these methods to the field of logical simulation has been reported by Case, et al2.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Reiss, R. F., "The Digital Simulation of Neuro-Muscular Organisms," Behavioral Science, p. 343-358; Oct., 1960.
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Case, P. W., Graff, H. H., Griffith, L. E., LeClercq, A. R., Murley, W. B., and Spence, T. M., "Solid Logic Design Automation," IBM J. Res. and Dev.; Apr., 1964.
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Newell, A., and Shaw, J. C., "Programming the Logic Theory Machine," Rand Publication P-954; 1957.
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Shaw, J. C., Newell, A., Simon, N. A., Ellis, T. O., "A Command Structure for Complex Information Processing," Proceedings Western Joint Computer Conference; 1958.
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CITED BY 19
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P. Agrawal , R. Tutundjian , W. Dally, Algorithms for accuracy enhancement in a hardware logic simulator, Proceedings of the 26th ACM/IEEE conference on Design automation, p.645-648, June 25-28, 1989, Las Vegas, Nevada, United States
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Stephen A. Szygenda , Edward W. Thompson, Fault insertion techniques and models for digital logic simulation, Proceedings of the December 5-7, 1972, fall joint computer conference, part II, December 05-07, 1972, Anaheim, California
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