Efficient partitioning of components

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Efficient partitioning of components

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 5th annual Design Automation Workshop table of contents

Washington, D. C., United States

Pages: 16.1 - 16.21

Year of Publication: 1968

Authors

Howard R. Charney	Raytheon Company, Space and Information Systems Division, Subdury, Massachusetts
Donald L. Plato	Raytheon Company, Space and Information Systems Division, Subdury, Massachusetts

Sponsors

IEEE : Institute of Electrical and Electronics Engineers
ACM: Association for Computing Machinery
SHARE : SHARE

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 3, Citation Count: 7

Additional Information:

abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper presents a technique for dividing a network of interconnecting components into groups of components so that the total number of interconnecting wires between groups tends to be minimized. The method of solution is noniterative, and provides good solutions using small amounts of computer time. The solution is based on the use of an electrical analogue which may be useful in aiding other design automation tasks.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Michle, W., "Link-Length Minimization in Networks," The Institute for Cooperative Research, University of Pennsylvania, 1957.
	2	F. B. Lavering, AUTO CARD automated printed circuit board design, Proceedings of the SHARE design automation workshop, p.9.1-9.29, January 1964 [doi>10.1145/800265.810745]
	3	Gamblin, R.L., Jacobs, M.Q., and Tunis, C.J., "Automatic Packaging of Miniaturized Circuits," Proc., The 1961 Circuit Packaging Symposium.
	4	Seshu, S., and Balabonian, N., "Linear Network Analysis," Wiley and Sons, Inc., 1959.

CITED BY 8

	R. L. Russo , P. K. Wolff, Sr., ALMS: Automated logic mapping system, Proceedings of the 8th workshop on Design automation, p.118-130, June 28-30, 1971, Atlantic City, New Jersey, United States
	Jason Cong , M'Lissa Smith, A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design, Proceedings of the 30th international conference on Design automation, p.755-760, June 14-18, 1993, Dallas, Texas, United States
	Kalapi Roy , Carl Sechen, A timing driven N-way chip and multi-chip partitioner, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.240-247, November 07-11, 1993, Santa Clara, California, United States
	D. M. Schuler , E. G. Ulrich, Clustering and linear placement, Papers on Twenty-five years of electronic design automation, p.50-56, June 1988
	Donald M. Schuler , Ernst G. Ulrich, Clustering and linear placement, Proceedings of the 9th workshop on Design automation, p.50-56, June 26-28, 1972
	Susan L. Taylor , Roderic Beresford , Theodore Sabety, Layout design—lessons from the Jedi designer (tutorial session), Proceedings of the 22nd ACM/IEEE conference on Design automation, p.337, June 1985, Las Vegas, Nevada, United States
	Tadakatsu Ishiga , Tokinori Kozawa , Shoji Sato, A logic partitioning procedure by interchanging clusters, Proceedings of the 12th conference on Design automation, p.369-377, January 1975
	D. J. Hatfield , J. Gerald, Program restructuring for virtual memory, IBM Systems Journal, v.10 n.3, p.168-192, September 1971