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Wire routing by optimizing channel assignment within large apertures
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 8th Design Automation Workshop table of contents
Atlantic City, New Jersey, United States
Pages: 155 - 169  
Year of Publication: 1971
Authors
Akihiro Hashimoto  Center for Advanced Computation, University of Illinois, Urbana, Illinois
James Stevens  Center for Advanced Computation, University of Illinois, Urbana, Illinois
Sponsors
ACM: Association for Computing Machinery
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IEEE : Institute of Electrical and Electronics Engineers
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 47,   Citation Count: 140
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ABSTRACT

The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
C. Y. Lee, "An algorithm for path connections and its applications", IRE Transactions on Electronic Computers, (September 1961), 346-365.
2
 
3
K. Mikami and K. Tabuchi, "A Computer Program for Optimal Routing of Printed Circuit Conductors." Proceedings of the IFIP Congress, 1968 Vol. 2 pp. 1475.
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6
R. P. Dilworth, "A Decomposition Theorem for Partially Ordered Sets," Ann. Math., (2) 51 (1950), 161-166.
 
7
A. Hashimoto and J. E. Stevens, "Path Cover of Acyclic Graphs", ILLIAC IV Document No. 239, December 24, 1970.
 
8
U. R. Kodres, "Formulation and solution of circuit card design problems through use of graph methods", in Advances in Electronics Circuit Packaging, Vol. 2, G. A. Walker, Ed., New York: Plenum 1962, 121-142.

CITED BY  140

Collaborative Colleagues:
Akihiro Hashimoto: colleagues
James Stevens: colleagues