| Wire routing by optimizing channel assignment within large apertures |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 8th Design Automation Workshop
table of contents
Atlantic City, New Jersey, United States
Pages: 155 - 169
Year of Publication: 1971
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Authors
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Akihiro Hashimoto
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Center for Advanced Computation, University of Illinois, Urbana, Illinois
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James Stevens
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Center for Advanced Computation, University of Illinois, Urbana, Illinois
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Downloads (6 Weeks): 2, Downloads (12 Months): 46, Citation Count: 140
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ABSTRACT
The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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C. Y. Lee, "An algorithm for path connections and its applications", IRE Transactions on Electronic Computers, (September 1961), 346-365.
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2
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3
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K. Mikami and K. Tabuchi, "A Computer Program for Optimal Routing of Printed Circuit Conductors." Proceedings of the IFIP Congress, 1968 Vol. 2 pp. 1475.
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4
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5
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6
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R. P. Dilworth, "A Decomposition Theorem for Partially Ordered Sets," Ann. Math., (2) 51 (1950), 161-166.
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7
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A. Hashimoto and J. E. Stevens, "Path Cover of Acyclic Graphs", ILLIAC IV Document No. 239, December 24, 1970.
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8
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U. R. Kodres, "Formulation and solution of circuit card design problems through use of graph methods", in Advances in Electronics Circuit Packaging, Vol. 2, G. A. Walker, Ed., New York: Plenum 1962, 121-142.
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CITED BY 141
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Gi-Joon Nam , Fadi Aloul , Karem Sakallah , Rob Rutenbar, A comparative study of two Boolean formulations of FPGA detailed routing constraints, Proceedings of the 2001 international symposium on Physical design, p.222-227, April 01-04, 2001, Sonoma, California, United States
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Chu-Yi Huang , Yen-Shen Chen , Youn-Long Lin , Yu-Chin Hsu, Data path allocation based on bipartite weighted matching, Proceedings of the 27th ACM/IEEE conference on Design automation, p.499-504, June 24-27, 1990, Orlando, Florida, United States
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Shigetoshi Nakatake , Keishi Sakanushi , Yoji Kajitani , Masahiro Kawakita, The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.418-425, November 08-12, 1998, San Jose, California, United States
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Jonathan Greene , Vwani Roychowdhury , Sinan Kaptanoglu , Abbas El Gamal, Segmented channel routing, Proceedings of the 27th ACM/IEEE conference on Design automation, p.567-572, June 24-27, 1990, Orlando, Florida, United States
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Ikuo Nishioka , Takuji Kurimoto , Hisao Nishida , Seiji Yamamoto , Toru Chiba , Toshiaki Nagakawa , Takatsugu Fujioka , Masashi Uchino, An automatic routing system for high density multilayer printed wiring boards, Proceedings of the 17th conference on Design automation, p.520-527, June 23-25, 1980, Minneapolis, Minnesota, United States
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K. R. Stevens , W. M. vanCleemput , T. C. Bennett , J. A. Hupp, Implementation of an interactive printed circuit design system, Proceedings of the 15th conference on Design automation, p.74-81, June 19-21, 1978, Las Vegas, Nevada, United States
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Ki-Wook Kim , Unni Narayanan , Sung-Mo Kang, Domino logic synthesis minimizing crosstalk, Proceedings of the 37th conference on Design automation, p.280-285, June 05-09, 2000, Los Angeles, California, United States
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C.-L. Ong , J.-T. Li , C.-Y. Lo, GENAC: an automatic cell synthesis tool, Proceedings of the 26th ACM/IEEE conference on Design automation, p.239-244, June 25-28, 1989, Las Vegas, Nevada, United States
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William A. Dees, Jr. , Robert J. Smith, II, Performance of interconnection rip-up and reroute strategies, Proceedings of the 18th conference on Design automation, p.382-390, June 29-July 01, 1981, Nashville, Tennessee, United States
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Raymond Y. Tsui , Robert J. Smith, II, A high-density multilayer PCB router based on necessary and sufficient conditions for single row routing, Proceedings of the 18th conference on Design automation, p.372-381, June 29-July 01, 1981, Nashville, Tennessee, United States
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Toru Chiba , Noboru Okuda , Takashi Kambe , Ikuo Nishioka , Tsuneo Inufushi , Seiji Kimura, SHARPS: A hierarchical layout system for VLSI, Proceedings of the 18th conference on Design automation, p.820-827, June 29-July 01, 1981, Nashville, Tennessee, United States
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Gi-Joon Nam , Karem A. Sakallah , Rob A. Rutenbar, Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.167-175, February 21-23, 1999, Monterey, California, United States
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Yung-Ching Hsieh , Chi-Yi Hwang , Youn-Long Lin , Yu-Chin Hsu, LiB: a cell layout generator, Proceedings of the 27th ACM/IEEE conference on Design automation, p.474-479, June 24-27, 1990, Orlando, Florida, United States
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L. F. Todd , J. M. Hansen , S. V. Pantulu , J. L. Barron , D. J. Gilbert , R. J. Anderson , A. K. Biyani, CGALA-a multi technology Gate Array Layout system, Proceedings of the 19th conference on Design automation, p.792-801, January 1982
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Goro Suzuki , Tetsuya Yamamoto , Kyoji Yuyama , Kotaro Hirasawa, MOSAIC: a tile-based datapath layout generator, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.166-170, November 1992, Santa Clara, California, United States
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Hiroshi Andou , Ichiro Yamamoto , Yuuko Mori , Yutaka Koike , Kimikatsu Shouji , Kazuyuki Hirakawa, Automatic routing algorithm for VLSI, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.785-788, June 1985, Las Vegas, Nevada, United States
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Y.-C. Chang , S.-C. Chang , L.-H. Hsu, Automated layout generation using gate matrix approach, Proceedings of the 24th ACM/IEEE conference on Design automation, p.552-558, June 28-July 01, 1987, Miami Beach, Florida, United States
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B. N. Tien , B. S. Ting , J. Cheam , K. Chow , S. C. Evans, GALA - an automatic layout system for high density CMOS gate arrays, Proceedings of the 21st conference on Design automation, p.657-662, June 25-27, 1984, Albuquerque, New Mexico, United States
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Min-Siang Lin , Hourng-Wern Perng , Chi-Yi Hwang , Youn-Long Lin, Channel density reduction by routing over the cells, Proceedings of the 28th conference on ACM/IEEE design automation, p.120-125, June 17-22, 1991, San Francisco, California, United States
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Koji Sato , Hiroyoshi Shimoyama , Takao Nagai , Masaru Ozaki , Toshihiko Yahara, A “grid-free” channel router, Proceedings of the 17th conference on Design automation, p.22-31, June 23-25, 1980, Minneapolis, Minnesota, United States
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Y. S. Kuo , T. C. Chern , Wei-kuan Shih, Fast algorithm for optimal layer assignment, Proceedings of the 25th ACM/IEEE conference on Design automation, p.554-559, June 12-15, 1988, Atlantic City, New Jersey, United States
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Tsung-Yi Ho , Chen-Feng Chang , Yao-Wen Chang , Sao-Jie Chen, Multilevel full-chip routing for the X-based architecture, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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Ki-Wook Kim , Seong-Ook Jung , Unni Narayanan , C. L. Liu , Sung-Mo Kang, Noise-aware power optimization for on-chip interconnect, Proceedings of the 2000 international symposium on Low power electronics and design, p.108-113, July 25-27, 2000, Rapallo, Italy
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|
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Isao Shirakawa , Noboru Okuda , Takashi Harada , Sadahiro Tani , Hiroshi Ozaki, A layout system for the random logic portion of MOS LSI, Proceedings of the 17th conference on Design automation, p.92-99, June 23-25, 1980, Minneapolis, Minnesota, United States
|
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|
|
|
|
|
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|
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|
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Chi-Yi Hwang , Yung-Ching Hsieh , Youn-Long Lin , Yu-Chin Hsu, An efficient layout style for 2-metal CMOS leaf cells and their automatic generation, Proceedings of the 28th conference on ACM/IEEE design automation, p.481-486, June 17-22, 1991, San Francisco, California, United States
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Douglas Braun , Jeffrey Burns , Srinivas Davadas , Hi Keung Ma , Kartikeya Mayaram , Fablo Romeo , Alberto Sangiovanni-Vincentelli, Chameleon: a new multi-layer channel router, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.495-502, July 1986, Las Vegas, Nevada, United States
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Sung-Chuan Fang , Kuo-En Chang , Wu-Shiung Feng , Sao-Jie Chen, Constrained via minimization with practical considerations for multi-layer VLSI/PCB routing problems, Proceedings of the 28th conference on ACM/IEEE design automation, p.60-65, June 17-22, 1991, San Francisco, California, United States
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Knut M. Just , Edgar Auer , Werner L. Schiele , Alexander Schwaferts, PALACE: a layout generator for SCVS logic blocks, Proceedings of the 27th ACM/IEEE conference on Design automation, p.468-473, June 24-27, 1990, Orlando, Florida, United States
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Shinichi Murai , Hiroo Tsuji , Morio Kakinuma , Kazumichi Sakaguchi , Chiyoji Tanaka, A hierarchical placement procedure with a simple blocking scheme, Proceedings of the 16th Conference on Design automation, p.18-23, June 25-27, 1979, San Diego, CA, United States
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|
|
|
|
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W. A. Dees , K. M. Parmar , A. Goyal , R. Y. Tsui , B. D. Rathi , R. J. Smith, II, A computer-aided VLSI layout system, Proceedings of the May 4-7, 1981, national computer conference, May 04-07, 1981, Chicago, Illinois
|
|
|
F. Balasa , P. G. Kjeldsberg , A. Vandecappelle , M. Palkovic , Q. Hu , H. Zhu , F. Catthoor, Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications, Journal of Signal Processing Systems, v.53 n.1-2, p.51-71, November 2008
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Cyrille Chavet , Caaliph Andriamisaina , Philippe Coussy , Emmanuel Casseau , Emmanuel Juin , Pascal Urard , Eric Martin, A design flow dedicated to multi-mode architectures for DSP applications, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
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