ALMS: Automated logic mapping system

ABSTRACT

ALMS is a set of design automation computer programs which accepts as input a description of a logic design, specifications of modules (e.g., chips, cards, etc.) into which the blocks of the design are to be partitioned or mapped, and some constraints that must be satisfied. It produces as output a documented assignment of the blocks to the modules satisfying the specified constraints. The system algorithms are presented, system features are discussed, program execution times are given and results are presented and compared to manual solutions for the same tasks. Three conclusions are reached. First is that computer programs make it possible to perform partitioning and mapping experiments which were not possible before. Second, for one-level partitions (e.g., logic gates on chips), highly automatic solutions obtained by the program are at least as good as manual solutions and are less costly to obtain. Third, for multi-level partitions (e.g., logic gates on chips on cards) or for mappings, the solutions obtained with the program are again at least as good as manual solutions; further-more, ALMS allows a designer to try more alternatives than he could manually, so that he can trade-off the time and cost of trying additional alternatives against the value of a better solution.

REFERENCES

• 1: Russo, R. L., P. H. Oden and P. K. Wolff, Sr., "A Heuristic Procedure for the Partitioning and Mapping of Computer Logic Graphs" to be published in the IEEE Transactions on Computers.
• 2: Howard R. Charney , Donald L. Plato, Efficient partitioning of components, Proceedings of the 5th annual workshop on Design automation, p.16.1-16.21, July 15-18, 1968, Washington, D. C., United States [doi>10.1145/800167.805401]
• 3: Notz, W. A., E. Schischa, J. L. Smith and M. G. Smith, "Large Scale Integration: Benefitting the System Designer", Electronics, pp 130-141, February 20, 1967.
• 4: Levy, S. Y., R. J. Linhardt, H. S. Muller, R. D. Sidnam, "System Utilization of Large-Scale Integration", IEEE Transactions on Electronic Computers, Vol. EC-16, No. 5, pp 562-566, October 1967.
• 5: Landman, B. S., R. L. Russo, "On a Pin vs. Block Relationship for Partitions of Logic Graphs", RC 3088, IBM T. J. Watson Research Center, Yorktown Heights, New York. (To be published in the IEEE Transactions on Computers.)
• 6: Khambata, A., "Introduction to Large Scale Integration", J. Wiley and Sons, 1969, p. 103.
• 7: Meade, R. M. and H. Geller, "System/360 Influence on the Design of Solid Logic Technology", Solid State Design/Circuit Design Engineering, July 1965.
• 8: Donath, W. E., "Hardware Implementation", Proc. of the 1968 Fall Joint Computer Conference.
• 9: Mennone, A. and R. L. Russo, "Experiments on Mapping of Computer Logic Graphs" to be published.
• 10: Orr, W. K., "Computer-Aided Design for Custom-Integrated System," Proc. of the 1969 Fall Joint Computer Conference.

INDEX TERMS

Primary Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

General Terms:
Design