TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic

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TEGAS2—anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 9th Design Automation Workshop table of contents

Pages: 116 - 127

Year of Publication: 1972

Author

S. A. Szygenda

Sponsors

IEEE : Institute of Electrical and Electronics Engineers
ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 7, Citation Count: 42

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper will attempt to consider requirements and problems encountered in the development of digital logic simulation and test generation systems. The procedure for doing this will be to first consider requirements and general considerations for a particular simulation system (TEGAS2(1,2)TEST GENERATION AND SIMULATION) and then to dissect the system into its major constituent parts with a discussion of adopted techniques and experiences. It is obvious that a detailed discussion of this sort would require far more space than permitted in these proceedings. Therefore, an attempt will be made to discuss the most important considerations for system design and development.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. A. Szygenda, D. Rouse, & E. Thompson, "A Model and Implementation of a Universal Time Delay Simulator for Large Digital Nets," AFIPS Proceedings of the SJCC, May, 1970.
	2	S. A. Szygenda, "A Simulator for Digital Design Verification and Diagnosis," Proceeding of the 1971 Lehigh Workshop on Reliability and Maintainability, December, 1971.
	3	Roth, J. P., "Diagnosis of Automata Failures: A Calculus and A Method", IBM Journal of Research & Development, Vol. 13, 1966.
	4	S. A. Szygenda, C. Hemming, D. Rouse, "Functional Simulation, A Basis for A Systems Approach to Digital Simulation and Fault Diagnosis," Proceedings of the Annual Summer Simulation Conference, June, 1972.
	5	S. A. Szygenda & G. Goldbogen, "Implementation & Extensions of Multi-Dimensional Path Sensitizing in a Simulation & Diagnosis System," Proceedings of the Seventh Annual Allerton Conference on Circuit and System Theory, Oct., 1969.

CITED BY 42

	Glenn R. Case , Jerry D. Stauffer, SALOGS-IV-A program to perform logic simulation and fault diagnosis, Proceedings of the 15th conference on Design automation, p.392-397, June 19-21, 1978, Las Vegas, Nevada, United States
	Yacoub M. El-ziq, A new test pattern generation system, Proceedings of the 17th conference on Design automation, p.62-68, June 23-25, 1980, Minneapolis, Minnesota, United States
	P. Agrawal , R. Tutundjian , W. Dally, Algorithms for accuracy enhancement in a hardware logic simulator, Proceedings of the 26th ACM/IEEE conference on Design automation, p.645-648, June 25-28, 1989, Las Vegas, Nevada, United States
	Hedayat Markus Bayegan , Einar Aas, An integrated system for interactive editing of schematics, logic simulation and PCB layout design, Proceedings of the 15th conference on Design automation, p.1-8, June 19-21, 1978, Las Vegas, Nevada, United States
	E. W. Thompson , N. Billawala, The software engineering technique of data hiding as applied to multi-level model implementation of logical devices in digital simulation, Proceedings of the 12th conference on Design automation, p.195-201, January 1975
	Cliff W. Hemming, Jr. , John M. Hemphill, Digital logic simulation models and evolving technology, Proceedings of the 12th conference on Design automation, p.85-94, January 1975
	P. Kozak , H. K. Gummel , B. R. Chawla, Operational features of an MOS timing simulator, Proceedings of the 12th conference on Design automation, p.95-101, January 1975
	E. W. Thompson , S. A. Szygenda, Three levels of accuracy for the simulation of different fault types in digital systems, Proceedings of the 12th conference on Design automation, p.105-113, January 1975
	D. Z. Zein , O. P. Engel , G. Ditlow, HLSIM—a new hierarchical logic simulator and netlist converter, Proceedings of the 29th ACM/IEEE conference on Design automation, p.432-437, June 08-12, 1992, Anaheim, California, United States
	E. W. Thompson , S. A. Szygenda , N. Billawala , R. Pierce, Timing analysis for digital fault simulation using assignable delays, Proceedings of the 11th workshop on Design automation, p.266-272, January 1974
	E. W. Thompson , S. A. Szygenda , N. Billawala , R. Pierce, Timing analysis for digital fault simulation using assignable delays, Papers on Twenty-five years of electronic design automation, p.324-330, June 1988
	Felix P. Mallmann, The management of engineering changes using the PRIMUS system, Proceedings of the 17th conference on Design automation, p.348-361, June 23-25, 1980, Minneapolis, Minnesota, United States
	Predrag G. Kovijanic, A new look at test generation and verification, Proceedings of the 14th conference on Design automation, p.58-63, January 1977
	Vighneswara Row Mokkarala , Antony Fan , Ravi Apte, A unified approach to simulation and timing verification at the functional level, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.757-761, June 1985, Las Vegas, Nevada, United States
	Peter Odryna , Kevin Nazareth , Carl Christensen, A workstation-mixed model circuit simulator, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.186-192, July 1986, Las Vegas, Nevada, United States
	Eric Schell , M. Ray Mercer, CADTOOLS: a CAD algorithm development system, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.658-666, June 1985, Las Vegas, Nevada, United States
	A. Miara , N. Giambiasi, Dynamic and deductive fault simulation, Proceedings of the 15th conference on Design automation, p.439-443, June 19-21, 1978, Las Vegas, Nevada, United States
	P. Wilcox , H. Rombeek, F/LOGIC - An interactive fault and logic simulator for digital circuits, Proceedings of the 13th conference on Design automation, p.68-73, June 28-30, 1976, San Francisco, California, United States
	Asad Karim , Stephen A. Szygenda, SMARTGEN: the implementation of an expert system for the generation of digital logic diagnostic tests, Proceedings of the 1st international conference on Industrial and engineering applications of artificial intelligence and expert systems, p.355-360, June 1988, Tullahoma, Tennessee, United States
	Wilfried Rottmann, An integrated system for computer design, Proceedings of the 12th conference on Design automation, p.8-14, January 1975
	M. A. d'Abreu , E. W. Thompson, An accurate functional level concurrent fault simulator, Proceedings of the 17th conference on Design automation, p.210-217, June 23-25, 1980, Minneapolis, Minnesota, United States
	William L. Keiner, Functional testing A user looks at logic simulation, Proceedings of the 10th workshop on Design automation, p.151-158, June 25-27, 1973
	Richard H. Lathrop , Robert S. Kirk, An extensible object-oriented mixed-mod functional simulation system, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.630-636, June 1985, Las Vegas, Nevada, United States
	T. McWilliams, Verification of timing constraints on large digital systems, Papers on Twenty-five years of electronic design automation, p.388-396, June 1988
	S. G. Chappell , P. R. Menon , J. F. Pellegrin , A. M. Schowe, Functional simulation in the lamp system, Proceedings of the 13th conference on Design automation, p.42-47, June 28-30, 1976, San Francisco, California, United States
	S. A. Szygenda , A. A. Lekkos, Integrated techniques for functional and gate-level digital logic simulation, Proceedings of the 10th workshop on Design automation, p.159-172, June 25-27, 1973
	P. Kozak , H. K. Gummel , B. R. Chawla, Operational features of a MOS timing simulator, Papers on Twenty-five years of electronic design automation, p.331-337, June 1988
	B. A. Prasad, Modelling techniques for dynamic logic and test pattern generation of a microprocessor, Proceedings of the Symposium on Design Automation and Microprocessors, p.100-107, February 24-25, 1977
	Steve Meyer, A data structure for circuit net lists, Proceedings of the 25th ACM/IEEE conference on Design automation, p.613-616, June 12-15, 1988, Atlantic City, New Jersey, United States
	W. M. vanCleemput, An hierarchical language for the structural description of digital systems, Proceedings of the 14th conference on Design automation, p.377-385, January 1977
	Thomas H. Krodel , Kurt J. Antreich, An accurate model for ambiguity delay simulation, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	William A. Johnson , Jeri Jane Crowley , J. D. Ray, Mixed-level simulation from a hierarchical CHDL, ACM SIGDA Newsletter, v.10 n.1, p.2-10, Jan. 1980
	C. W. Hemming , S. A. Szygenda, Modular requirements for digital logic simulation at a predefined functional level, Proceedings of the ACM annual conference, August 01-01, 1972, Boston, Massachusetts, United States
	Steve Meyer, CAD tool interchangeability through Net list translation, ACM SIGDA Newsletter, v.20 n.1, p.51-59, June 1990
	Thomas M. McWilliams, Verification of timing constraints on large digital systems, Proceedings of the 17th conference on Design automation, p.139-147, June 23-25, 1980, Minneapolis, Minnesota, United States
	Donald M. Schuler , Roger K. Cleghorn, An efficient method of fault simulation for digital circuits modeled from boolean gates and memories, Proceedings of the 14th conference on Design automation, p.230-238, January 1977
	C. W. Hemming , S. A. Szygenda, Modular requirements for digital logic simulation at a predefined functional level, ACM SIGDA Newsletter, v.2 n.2-3, p.4-16, September 1972
	Glenn R. Case, Computer-aided design of electrical circuits Simulation techniques (A Tutorial), Proceedings of the ACM '81 conference, p.199-203, January 1981
	Mark J. Flomenhoft , Brenda M. Csencsits, A minicomputer-based logic circuit fault simulator, ACM SIGDA Newsletter, v.4 n.3, p.15-19, September 1974
	S. A. Szygenda , A. Lekkos , J. Fike, Implemented techniques for handling spikes in an assignable delay simulator, Proceedings of the 7th conference on Winter simulation, p.721-722, January 14-16, 1974, Washington, DC
	N. Giambiasi , A. Miara , D. Muriach, SILOG: A practical tool for large digital network simulation, Proceedings of the 16th Conference on Design automation, p.263-271, June 25-27, 1979, San Diego, CA, United States
	Stephen A. Szygenda , Edward W. Thompson, Fault insertion techniques and models for digital logic simulation, Proceedings of the December 5-7, 1972, fall joint computer conference, part II, December 05-07, 1972, Anaheim, California