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ABSTRACT
PLAC is a multi-algorithm, 2-dimensional placement program which accommodates many of the “real world” constraints which occur in the layout of electrical circuits. PLAC was implemented as part of LTX [1], a general integrated circuit layout system, but is capable of handling circuit layout tasks from other technologies (e.g., PC boards, ceramic substrates). PLAC interlaces constructive initial placement with iterative pairwise exchange, using an approximation of total routing length as the primary figure-of-merit. The layout designer can influence the placement by providing a “seed” preplacement of key cells. PLAC results are given for a DIP board layout and two polycell integrated circuit layouts. Comparisons are made to other semi-automatic and manual placement procedures. Running time on an HP21MX minicomputer ranged from 4 minutes on a 34-cell problem to 1 hour on a 511-cell problem.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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G. Persky , D. N. Deutsch , D. G. Schweikert, LTX - a system for the directed automatic design of LSI circuits, Proceedings of the 13th conference on Design automation, p.399-407, June 28-30, 1976, San Francisco, California, United States
[doi> 10.1145/800146.804840]
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G.W.Smith,Jr., "Net-span minimization: an N-dimensional placement optimization criteria", internal BTL memorandum, 1 Nov 1972.
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R.L.Mattison, private communication.
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CITED BY 8
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R. Malladi , G. Serrero , A. Verdillon, Automatic placement of rectangular blocks with the interconnection channels, Proceedings of the 18th conference on Design automation, p.419-425, June 29-July 01, 1981, Nashville, Tennessee, United States
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G. Persky , C. Enger , D. M. Selove, The Hughes Automated Layout System - automated LSI/VLSI layout based on channel routing, Proceedings of the 18th conference on Design automation, p.22-28, June 29-July 01, 1981, Nashville, Tennessee, United States
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Shinichi Murai , Hiroo Tsuji , Morio Kakinuma , Kazumichi Sakaguchi , Chiyoji Tanaka, A hierarchical placement procedure with a simple blocking scheme, Proceedings of the 16th Conference on Design automation, p.18-23, June 25-27, 1979, San Diego, CA, United States
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