An accurate time delay model for large digital network simulation

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An accurate time delay model for large digital network simulation

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 13th Design Automation Conference table of contents

San Francisco, California, United States

Pages: 54 - 60

Year of Publication: 1976

Authors

C. Chicoix
J. Pedoussat
N. Giambiasi

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\DATC : IEEE Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 2, Citation Count: 7

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ABSTRACT

The authors propose a three valued model for temporal simulation of logic system. This model is well suited for analysis of hazards and high frequency rejection phenomenas. By using a new temporal model, we avoid backtracking or anticipation techniques (generally used in other models) and allow very simple implementation. The model and the mains algorithms are presented in detail in the paper and some examples including hazards are given.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Michael Yoeli , Shlomo Rinon, Application of Ternary Algebra to the Study of Static Hazards, Journal of the ACM (JACM), v.11 n.1, p.84-97, Jan. 1964 [doi>10.1145/321203.321214]
	2	E. W. Thompson , S. A. Szygenda, Three levels of accuracy for the simulation of different fault types in digital systems, Proceedings of the 12th conference on Design automation, p.105-113, January 1975
	3	Irvin H Yetter, High-speed fault simulation for UNIVAC 1107 computer system, Proceedings of the 1968 23rd ACM national conference, p.265-277, August 27-29, 1968 [doi>10.1145/800186.810587]
	4	J. S. JEPHSON - R. P. Mc QUARRIE - R. E. VOGELSBERG "A three value computer design verification system" IBM Journal - Vol 8 - 1969
	5	S. G. CHAPPEL - S. S. YAU "Simulation of large asynchronous logic circuits using an ambiguous gate model" Fall Joint Computer Conference - 1971
	6	J. CLAPIER-PEDOUSSAT "Modèle mathématique d'analyse du comportement dynamique des systèmes logiques - Application à la C. A. O." Thèse Docteur 3ème Cycle - Montpellier - Juillet 1975
	7	Contrat D. G. R. S. T. n°. 73.7.1391 "Comportement dynamique des ensembles logiques complexes"

CITED BY 7

	A. Miara , N. Giambiasi, Dynamic and deductive fault simulation, Proceedings of the 15th conference on Design automation, p.439-443, June 19-21, 1978, Las Vegas, Nevada, United States
	T. McWilliams, Verification of timing constraints on large digital systems, Papers on Twenty-five years of electronic design automation, p.388-396, June 1988
	Norbert Giambiasi , Bruno Escude , Sumit Ghosh, Generalized discrete event simulation of dynamic systems, Transactions of the Society for Computer Simulation International, v.18 n.4, p.216-229, December 2001
	Thomas H. Krodel , Kurt J. Antreich, An accurate model for ambiguity delay simulation, Proceedings of the conference on European design automation, March 12-15, 1990, Glasgow, Scotland
	N. Giambiasi , A. Miara , D. Muriach, Methods for generalized deductive fault simulation, Proceedings of the 17th conference on Design automation, p.386-392, June 23-25, 1980, Minneapolis, Minnesota, United States
	Thomas M. McWilliams, Verification of timing constraints on large digital systems, Proceedings of the 17th conference on Design automation, p.139-147, June 23-25, 1980, Minneapolis, Minnesota, United States
	N. Giambiasi , A. Miara , D. Muriach, SILOG: A practical tool for large digital network simulation, Proceedings of the 16th Conference on Design automation, p.263-271, June 25-27, 1979, San Diego, CA, United States