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ABSTRACT
The concept of the genealogical approach to the layout problem is presented. The system pursues the idea of flexible modules and is capable of dealing with arbitrarily complex tasks. The genealogical tree of the system provides a mainframe for organizing the information flow. Results of the system routines are described in terms of transitions between flexibility classes of modules.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Koji Sato , Takao Nagai , Hiroyoshi Shimoyama , Toshihiko Yahara, MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks, Proceedings of the 16th Conference on Design automation, p.297-304, June 25-27, 1979, San Diego, CA, United States
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K. Kani et al., "ROBIN, a building block LSI routing program", Proc. ISCAS, pp. 658-661, 1976.
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H. Kawanishi et al., "A routing method of building block LSI", Proc. 7-th Asilomar Conf. on Circ. Syst. and Comp., pp.119-123, 1973.
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K. Sato and T. Nagai, "A method of specifying the relative locations between blocks in a routing program for building block LSI", Proc. ISCAS, pp.673-676, 1979.
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B.T. Preas and W.M. van Cleemput, "Routing algorithms for arbitrary shaped blocks", Proc. ISCAS, pp.482-485, 1979.
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R. Keyes, "The evolution of digital electronics towards VLSI", IEEE Journal of Solid State Circuits, vol. SC-14, no.2, pp.193-201, April 1979.
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W.R. Heller et al., "Prediction of wiring space requirements for LSI", Journal of Design Automation and Fault Tolerant Computing, vol.2, no.2, pp. 117-144, May 1978.
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R.H.J.M. Otten and A.A. Szepieniec, "Graph oriented approach to the layout problem", Proc. ISCAS, 1980.
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CITED BY 12
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Rathin Putatunda , David Smith , Stephen McNeary , James Crabbe, HAPPI: a chip compiler based on double-level-metal technology, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.736-743, July 1986, Las Vegas, Nevada, United States
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P. Rao , R. Ramnarayan , G. Zimmermann, Spider, a chip planner for ISL technology, Proceedings of the 21st conference on Design automation, p.665-666, June 25-27, 1984, Albuquerque, New Mexico, United States
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