Efficient placement and routing techniques for master slice LSI

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Efficient placement and routing techniques for master slice LSI

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 17th Design Automation Conference table of contents

Minneapolis, Minnesota, United States

Pages: 458 - 464

Year of Publication: 1980

ISBN:0-89791-020-6

Authors

Hiroshi Shiraishi
Fumiyasu Hirose

Sponsors

IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 7, Citation Count: 12

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper deals with placement and routing techniques for master slice LSIs. The basic idea of both techniques is to make wiring density on the chip more uniform. Algorithms and some experimental results are described.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Hannan, M. and J.M. Kurtzberg, "Placement Techniques", Chap. 5 in Design Automation of Digital Systems; Theory and Techniques, vol. 1, M.A. Breuer, ed., Prentice-Hall, pp213-282, 1972
	2	Hannan, M, P.K. Wolff and B.J. Anguli, "A Study of Placement Techniques", J. of Design Automation and Fault Tolerant Computing, vol. 1, Oct. 1976, pp 28-61
	3	K. H. Khokhani , A. M. Patel, The chip layout problem: A placement procedure for lsi, Proceedings of the 14th conference on Design automation, p.291-297, January 1977
	4	K. A. Chen , M. Feuer , K. H. Khokhani , N. Nan , S. Schmidt, The chip layout problem: An automatic wiring procedure, Proceedings of the 14th conference on Design automation, p.298-302, January 1977
	5	Breuer, M.A., "Min-Cut Placement", J. of Design Automation and Fault-Tolerant Computing, Oct. 1977, pp 343-362
	6	Lorretta I. Corrigan, A placement capability based on partitioning, Proceedings of the 16th Conference on Design automation, p.406-413, June 25-27, 1979, San Diego, CA, United States
	7	Kerninghan, B.W. and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs", Bell System Technical Journal, vol. 49, 1970, pp. 291-307
	8	D. G. Schweikert , B. W. Kernighan, A proper model for the partitioning of electrical circuits, Proceedings of the 9th workshop on Design automation, p.57-62, June 26-28, 1972 [doi>10.1145/800153.804930]
	9	G. Persky, PRO - an automatic string placement program for polycell layout, Proceedings of the 13th conference on Design automation, p.417-424, June 28-30, 1976, San Francisco, California, United States [doi>10.1145/800146.804842]
	10	Asano, T., T. Kitahashi, K. Tanaka, H. Horino and N. Amano, "A Wire-Routing Scheme Based on TrunkDivision Methods", IEEE Trans. on Computers, Aug. 1977, pp. 764-772
	11	Akihiro Hashimoto , James Stevens, Wire routing by optimizing channel assignment within large apertures, Proceedings of the 8th workshop on Design automation, p.155-169, June 28-30, 1971, Atlantic City, New Jersey, United States [doi>10.1145/800158.805069]
	12	David N. Deutsch, A “Dogleg” channel router, Proceedings of the 13th conference on Design automation, p.425-433, June 28-30, 1976, San Francisco, California, United States [doi>10.1145/800146.804843]
	13	Tatsuya Kawamoto , Yoji Kajitani, The minimum width routing of A 2-row 2-layer polycell-layout, Proceedings of the 16th Conference on Design automation, p.290-296, June 25-27, 1979, San Diego, CA, United States
	14	Murano, K., Y. Mochida, F. Amano and T. Kinoshita, "Multiprocessor Architecture for Voiceband Data Processing (Application to 9600 BPS MODEM)", ICC(1979), pp.37.3.1-37.3.5

CITED BY 12

	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	R. Nair , S. J. Hong , S. Liles , R. Villani, Global wiring on a wire routing machine, Papers on Twenty-five years of electronic design automation, p.248-255, June 1988
	Mark R. Hartoog, Analysis of placement procedures for VLSI standard cell layout, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.314-319, July 1986, Las Vegas, Nevada, United States
	Masayuki Terai , Kazuhiro Takahashi , Koji Sato, A new min-cut placement algorithm for timing assurance layout design meeting net length constraint, Proceedings of the 27th ACM/IEEE conference on Design automation, p.96-102, June 24-27, 1990, Orlando, Florida, United States
	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Papers on Twenty-five years of electronic design automation, p.241-247, June 1988
	K. Shahookar , P. Mazumder, VLSI cell placement techniques, ACM Computing Surveys (CSUR), v.23 n.2, p.143-220, June 1991
	Akihiko Yamada, Design automation status in Japan, Proceedings of the 18th conference on Design automation, p.43-50, June 29-July 01, 1981, Nashville, Tennessee, United States
	Ravi Nair , Se June Hong , Sandy Liles , Ray Villani, Global wiring on a wire routing machine, Proceedings of the 19th conference on Design automation, p.224-231, January 1982
	Kazuhiro Takahashi , Kazuo Nakajima , Masayuki Terai , Koji Sato, Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.428-431, November 06-10, 1994, San Jose, California, United States
	Howard E. Krohn, An over-cell gate array channel router, Proceedings of the 20th conference on Design automation, p.665-670, June 27-29, 1983, Miami Beach, Florida, United States
	Matthew Sacker , Andrew D. Brown , Andrew J. Rushton , Peter R. Wilson, A behavioral synthesis system for asynchronous circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.9, p.978-994, September 2004
	Steve Meyer, A new placement level wirability estimate with measurements, ACM SIGDA Newsletter, v.20 n.2, p.25-39, Oct. 1990