The Standard Transistor Array (star) (Part II automatic cell placement techniques)

ABSTRACT

Layout of a STAR device consists of the placement of standard cells (circuit elements) on the array and the routing of conductors between cells. Cell placement must be such that routing is not hindered. Also, placement procedures must be cost effective and easy to implement on a digital computer. A placement procedure for STARs is described in this paper that satisfies these characteristics. The procedure attempts to optimize the placement with respect to several criteria including expected routing channel usage and routing VIA requirements. Computer implementations of the procedure are discussed. Experimental results are presented which indicate that the procedure yields near-optimum results in computationally convenient amounts of time.

REFERENCES

• 1: John M. Gould , Teddy M. Edge, The standard transistor array (STAR): Part I A two-layer metal semicustom design system, Proceedings of the 17th conference on Design automation, p.108-113, June 23-25, 1980, Minneapolis, Minnesota, United States [doi>10.1145/800139.804519]
• 2: R. A. Wright, Research Study: Device Technology,STAR Router User's Guide, NASA Contractors Report, Number NASA CR-161213, February 27, 1979.
• 3: A. Feller, Automatic layout of low-cost quick-turnaround random-logic custom LSI devices, Proceedings of the 13th conference on Design automation, p.79-85, June 28-30, 1976, San Francisco, California, United States [doi>10.1145/800146.804799]
• 4: Glenn William Cox, Automated cell placement techniques for the standard transistor array (star)., 1979
• 5: Donald M. Schuler , Ernst G. Ulrich, Clustering and linear placement, Proceedings of the 9th workshop on Design automation, p.50-56, June 26-28, 1972 [doi>10.1145/800153.804929]
• 6: M. Hanan, P. Wolff, and B. Agule, "A Study of Placement Techniques," Journal of Design Automation and Fault-Tolerant Computing, Vol. 1, No. 1, October 1976, pp. 28-61.
• 7: M. Hanan and J. Kurtzberg, "Placement Techniques," Chapter 5 in Design Automation of Digital Systems: Volume 1, Theory and Techniques, M. A. Breuer, ed., Prentice-Hall, Inc., Englewood Cliffs, NJ, 1972.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Placement and routing

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Logic arrays

General Terms:
Design