Processor-memory interconnections for multiprocessors

ABSTRACT

A new class of interconnection networks is proposed for processor to memory communication in multiprocessing systems. These networks allow a direct link between any processor to any memory module. The cost of these networks is considerably less than that of full crossbars. Moreover, the design and control of these networks is simple. The proposed networks and the full crossbars are analyzed with respect to the bandwidth and the cost.

REFERENCES

• 1: D. H. Lawrie, "Access and Alignment of Data in an Array Processor", IEEE Trans. Comput., Vol. C-24, pp. 1145-1155, Dec. 1975.
• 2: M. C. Pease, "The Indirect Binary n-Cube Microprocessor Array", IEEE Trans. Comput., Vol. C-26, pp. 458-473, May 1977.
• 3: Howard Jay Siegel , S. Diane Smith, Study of multistage SIMD interconnection networks, Proceedings of the 5th annual symposium on Computer architecture, p.223-229, April 03-05, 1978 [doi>10.1145/800094.803052]
• 4: H. S. Stone, "Parallel Processing with the Perfect Shuffle", IEEE Trans. Comput., Vol. C-20, pp. 153-161, Feb. 1971.
• 5: V. E. Benes, Mathematical Theory of Connecting Networks and Telephone Traffic, Academic Press, New York, 1965.
• 6: D. Y. Chang, D. J. Kuck and D. H. Lawrie, "On the Effective Bandwidth of Parallel Memories", IEEE Trans. Comput., Vol. C-26, pp. 480-490, May 1977.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES

  D. Software
  D.4 OPERATING SYSTEMS
      D.4.1 Process Management
          Subjects: Multiprocessing/multiprogramming/multitasking

General Terms:
Design, Performance