The architecture of the SPERRY UNIVAC 1100 series systems

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The architecture of the SPERRY UNIVAC 1100 series systems

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International Symposium on Computer Architecture archive
Proceedings of the 6th annual symposium on Computer architecture table of contents

Pages: 137 - 146

Year of Publication: 1979

Authors

B. R. Borgerson
M. D. Godfrey
P. E. Hagerty
T. R. Rykken

Sponsors

IEEE : Institute of Electrical and Electronics Engineers
ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 18, Citation Count: 4

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ABSTRACT

This paper presents an overview of the architecture of the SPERRY UNIVAC® 1100 Series systems. The principal topics are instruction and data formats, main storage and addressing, process management, and I/O.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

B. R. Borgerson , M. L. Hanson , P. A. Hartley, The evolution of the Sperry Univac 1100 series: a history, analysis, and projection, Communications of the ACM, v.21 n.1, p.25-43, Jan. 1978 [doi>10.1145/359327.359334]

CITED BY 4

	John Tartar, Multiprocessor hardware: An architectural overview, Proceedings of the ACM 1980 annual conference, p.518-526, January 1980
	M. R. Bhujade, On the design of Always Compatible Instruction Set Architecture(ACISA), ACM SIGARCH Computer Architecture News, v.11 n.5, p.28-30, December 1983
	Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982
	M. Smotherman, A sequencing-based taxonomy of I/0 systems and review of historical machines, ACM SIGARCH Computer Architecture News, v.17 n.5, p.5-15, Sep. 1989