A bit-slice cache controller

ABSTRACT

Cache storage is a proven memory speedup technique in large mainframe computers. Two of the main difficulties associated with the use of this concept in small machines are the high relative cost and complexity of the cache controller. An LSI bit-slice chip set is described which should reduce both controller cost and complexity. The set will enable a memory designer to construct a wide variety of cache structures with a minimum number of components and interconnections. Design parameters are based on the results of extensive simulation. Particular emphasis is placed on the need for design flexibility. The chip set consists of three devices - an address bit-slice, a data bit-slice and a central control unit. Circuit design has been completed to a gate level based on an ECL/EFL implementation. The proposed structure will accommodate cache sizes up to 2K words with access times as short as 25 ns.

REFERENCES

• 1: B. D. Ackland and D. A. Pucknell, "Studies of Cache Store Behavior in a Real Time Minicomputer Environment." Electronics Letters, Vol. 11, No. 24, November 1975, pp. 588-590.
• 2: B. D. Ackland, "Cache Store Concepts in Small High-Speed Computers." Ph.D. Thesis, Department of Electrical Engineering, University of Adelaide, June 1978.
• 3: J. Bell, D. Casasent and C. G. Bell, "An Investigation of Alternative Cache Organizations." I.E.E.E. Trans. on Computers, C-23, 4, April 1974, pp. 346-351.
• 4: WILLIAM D. STRECKER, Cache memories for PDP-11 family computers, Proceedings of the 3rd annual symposium on Computer architecture, p.155-158, January 19-21, 1976
• 5: C. J. Conti, "Concepts for Buffer Storage." Computer Group News, 2, 3, March 1969, pp. 9-13.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

General Terms:
Design, Performance