A general multi-microprocessor interconnection mechanism for non-numeric processing

ABSTRACT

MMPS interconnection problems are discussed in terms of a single time-shared bus. The performance drawbacks usually associated with the single bus alternative are attributed to the high bus utilization at the basic building block level. The Pended Transaction Bus protocol is presented as a general solution to such utilizations. Such a bus is developed to support more than 50 processors without severe contention. The basic protocol of the MC68000 as a current generation microprocessor is investigated, and shown ineffective for true multi-microprocessor systems.

REFERENCES

• 1: Enslow, P.H. Jr., "Multiprocessor Architecture-A Survey," (invited paper) 1975 Segamore Computer Conference on Parallel Processing, pp. 63-70.
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• 15: Toong, Hoo-min D., work in progress, to be published.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

Additional Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS

General Terms:
Performance