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The entropic limitations on VLSI computations(Extended Abstract)
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Source Annual ACM Symposium on Theory of Computing archive
Proceedings of the thirteenth annual ACM symposium on Theory of computing table of contents
Milwaukee, Wisconsin, United States
Pages: 308 - 311  
Year of Publication: 1981
Author
Sponsor
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
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ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 16,   Citation Count: 22
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ABSTRACT

In this paper we will explore the limitations imposed by entropic constraints, both in generality and for specific problems. We list below the main questions that we will address. (1) In the binary number system, addition is easy while multiplication is hard for VLSI. Is there an “ideal” number representation, in which all arithmetic operations have efficient VLSI implementations? (2) Can one build multipliers for binary numbers, which achieve both small area and fast average computation time? (3) Thompson's technique applies only to multiple output functions. How can one prove area-time bounds for single output functions? (4) What other ways are there for deriving entropic constraints from consideration of data movement? Answers to these questions will be discussed in the ensuing sections.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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R. P. Brent and L. M. Goldschlager, "Some area-time tradeoffs for VLSI," August 1980, draft.
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R. P. Brent and H. T. Kung, "On the area of binary tree layouts," Information Processing Letters 11 (1980), 46-48.
 
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L.J. Guibas, H. T. Kung, and C. D. Thompson, "Direct VLSI implementation of combinatorial algorithms," Proc. Conf. on VLSI Architecture Design and Fabrication, 1979, CALTECH.
 
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J. E. Hopcroft and R. M. Karp, "An n5/2 algorithm for maximum matchings in bipartite graphs," SIAM J. on Computing 2(1973), 225-231.
 
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H. T. Kung and C. E. Leiserson, "Systolic arrays for VLSI," in the book by Mead and Conway (reference {8}), Section 8.3.
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A. L. Rosenberg, private communication, March 1980.
 
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J. E. Savage, "Area-time tradeoffs for matrix multiplication and related problems in VLSI models," Proc. 17-th Ann. Allerton Conf. on Comm., Control and Computing, October 1979, Allerton, Illinois.
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J. Vuillemin, "A combinatorial limit to the computing power of VLSI circuits," Proc. 21-st Ann. IEEE Symp. on Foundations of Computer Science, October 1980, Syracuse, New York, 294-300.
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CITED BY  22