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A multi-processor reduction machine for user-defined reduction languages.
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Source International Symposium on Computer Architecture archive
Proceedings of the 7th annual symposium on Computer Architecture table of contents
La Baule, United States
Pages: 121 - 130  
Year of Publication: 1980
Authors
Sponsors
IEEE-CS : Computer Society
SIGARCH: ACM Special Interest Group on Computer Architecture
AFCET : Assoc Francaise des Sciences
INRIA : Institut Natl de Recherche en Info et en Automatique
SEE : Société des Electriciens et des Electroniciens
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 21,   Citation Count: 7
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ABSTRACT

The design of a multi-processor reduction machine, supporting a class of user-defined reduction languages, is presented. A reduction machine is based on a “by need” or demand driven model of computation in which an instruction is executed only when a result it generates is requested. In such a machine, an instruction is a (variable length and possibly nested) expression and the machine language is referred to as a reduction language. In the multi-processor reduction machine presented, the asynchronous operation of a processor is controlled by a swappable, user-defined, state transition table. Each table supports a particular reduction language. To ensure the harmonious operation of the processors a state transition table is generated automatically for a user, in a similar way that a parser generator is used to generate table driven parsers.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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E.I. Organick, "New Directions in Computer Systems Architecture". Euromicro Journal, Vol. 5, No. 4 (July 1979), pp. 190-202.
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R.P. Hopkins, P.W. Rautenbach and P.C. Treleaven, "A Computer Supporting Data Flow, Control Flow and Updateable Memory". Tech. Report 144, Computing Laboratory, University of Newcastle upon Tyne (September 1979).
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W.E. Kluge, "The Architecture of a Reduction Language Machine Hardware Model". Tech. Report ISF-Report 79.03, Gesellschaft fur Mathematik und Datenverarbeitung MBH Bonn (August 1979).
 
14
G.A. Mago, "A Network of Microprocessors to Execute Reduction Languages". Int. Journ. of Computer and Information Sciences, Vol. 8, No. 5 and Vol. 8, No. 6 (1979).
 
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R.M. Keller, et al, "A Loosely-coupled Applicative Multi-processing System". AFIPS Conf. Proc. Vol. 48 (1979) pp. 861-870.
 
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S.S. Patil and T.A. Welch, "A Programmable Logic Approach for VLSI". IEEE Trans. on Computers, Vol. C-28, No. 9 (September 1979) pp.594-601.
 
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J. Backus, "Reduction Languages and Variable Free Programming". IBM Research, RJ 1010 (April 1972).
 
18
J. Backus, "Programming Languages and Closed Applicative Languages". IBM Research RJ 1245 (July 1973).
 
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20
G.F. Mole, "A Multi-processor Reduction Machine for executing User-defined Reduction Languages". M.Sc. Dissertation, University of Newcastle upon Tyne (submitted).


Collaborative Colleagues:
Philip C. Treleaven: colleagues
Geoffrey F. Mole: colleagues