Timed Petri nets and preliminary performance evaluation

ABSTRACT

It is shown that the behavior of a certain class of timed Petri nets can be represented by a finite labeled directed graph in which the labels describe times and probabilities of transitions between vertices of the graph. Further analysis of such a graph can be done by techniques known for Markov chains. The method is applied to evaluation of some performance indices for two simple processor architectures. The timed Petri nets modeling the processors are shown and the resulting performance indices are compared. Some other architectures are discussed shortly.

REFERENCES

• 1: Ghosh S.: Some comments on timed Petri nets; Journeés sur les réseaux de Petri, Paris 1977.
• 2: Lorin H.: Parallelism in hardware and software - real and apparent concurrency; Prentice-Hall 1972.
• 3: James L. Peterson, Petri Nets, ACM Computing Surveys (CSUR), v.9 n.3, p.223-252, Sept. 1977 [doi>10.1145/356698.356702]
• 4: C. Ramchandani, ANALYSIS OF ASYNCHRONOUS CONCURRENT SYSTEMS BY TIMED PETRI NETS, Massachusetts Institute of Technology, Cambridge, MA, 1974
• 5: Joseph Sifakis, Use of Petri Nets for Performance Evaluation, Proceedings of the Third International Symposium on Measuring, Modelling and Evaluating Computer Systems, p.75-93, October 03-05, 1977
• 6: Zuberek W.: Analysis and some methods of increasing the effectiveness of central processing units (in Polish); ISTEI Report 26, Warsaw 1979.

INDEX TERMS

Primary Classification:
  D. Software
  D.2 SOFTWARE ENGINEERING
      D.2.2 Design Tools and Techniques
          Subjects: Petri nets

Additional Classification:
  H. Information Systems
  H.3 INFORMATION STORAGE AND RETRIEVAL
      H.3.4 Systems and Software
          Subjects: Performance evaluation (efficiency and effectiveness)

General Terms:
Design, Performance