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A multiple stream microprocessor prototype system: AMP-1
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Source International Symposium on Computer Architecture archive
Proceedings of the 7th annual symposium on Computer Architecture table of contents
La Baule, United States
Pages: 9 - 16  
Year of Publication: 1980
Author
Sponsors
IEEE-CS : Computer Society
SIGARCH: ACM Special Interest Group on Computer Architecture
AFCET : Assoc Francaise des Sciences
INRIA : Institut Natl de Recherche en Info et en Automatique
SEE : Société des Electriciens et des Electroniciens
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 9,   Downloads (12 Months): 18,   Citation Count: 4
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ABSTRACT

A general-purpose multiple-stream processor with shared memory and a single time-multiplexed synchronous bus has been implemented. The AMP-1 system uses eight standard microprocessors and 64K bytes of memory. The design is highly efficient in the use of processor, bus, and memory resources. Preliminary performance measurements agree closely with an analytic memory access conflict model and show extremely low conflict-based performance degradation. Heavy interleaving of the memory and effective multitasking of a job can yield significant performance speedups. Considerations for future implementations are presented.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
S. M. Thatte and J. A. Abraham, "Test Generation for General Microprocessor Architectures," Proc. 9th International Symposium on Fault-Tolerant Computing, Madison, Wisconsin, June 20-22, 1979, pp. 203-210.
 
2
J. A. Abraham and G. Metze, "Roving Diagnosis for High Performance Digital Systems," Proc. 1978 Conf. on Information Sciences and Systems, The Johns Hopkins University, Baltimore, Maryland, March 29-31, 1978, pp. 221-226.
 
3
F. A. Briggs and E. S. Davidson, "Organization of Semiconductor Memories for Parallel-Pipelined Processors," IEEE-TC, Feb. 1977, pp. 162-169
 
4
J. Emer, "Shared Resources for Multiple Instruction Stream Pipelined Processors," Coordinated Science Laboratory Report R-838, March 1979.
 
5
W. J. Kaminsky and E. S. Davidson, "Developing a Multiple Stream Single Chip Processor," Computer, Dec. 1979, pp. 66-76.
 
6
W. J. Kaminsky, "Architecture for Multiple Instruction Stream LSI Processors," Coordinated Science Laboratory Report R-796, Oct. 1977.
 
7
J. S. Emer and E. S. Davidson, "Control Store Organization for Multiple Stream Pipelined Processors," Proc. 1978 Int'l Conf. on Parallel Processing, pp. 43-48.
 
8
E. S. Davidson, L. E. Shar, A. T. Thomas, and J. H. Patel, "Effective Control for Pipelined Computers," Proc. Compcon Spring, 1975, pp. 181-184.
 
9
R. J. Swan, S. H. Fuller, and D. P. Siewiorek, "Cm*-A modular, multimicroprocessor," Proc. NCC, 1977, pp. 637-644.
 
10
R. L. Budzinski, "Dynamic Memory Allocation for a Virtual Memory Computer," Coordinated Science Laboratory Report R-754, Jan. 1977
11
 
12
D. W. Hammerstrom, "Analysis of Memory Addressing Architecture," Coordinated Science Laboratory Report R-777, July 1977.
 
13
W. Abu-Sufah, "Improving the Performance of Virtual Memory Computers," Department of Computer Science Report R-78-945, University of Illinois, Nov. 1978.