Asynchronous and clocked control structures for VLSI based interconnection networks

ABSTRACT

A central issue in the design of multiprocessor systems is the interconnection network which provides communications paths between the processors. For large systems, high bandwidth interconnection networks will require numerous 'network chips' with each chip implementing some subnetwork of the original larger network. Modularity and growth are important properties for such networks since multiprocessor systems may vary in size. This paper is concerned with the question of timing control of such networks. Two approaches, asynchronous and clocked, are used in the design of a basic network switching module. The modules and the approaches are then modelled and equations for network time delay are developed. These equations form the basis for a comparison between the two approaches. The importance of clock distribution strategies and clock skew is quantified, and a network clock distribution scheme which guarantees equal length clock paths is presented.

REFERENCES

• 1: Anantharaman, S. Delays in PLAs: Analysis, Reduction and Computer Aided Optimization. M.S. Thesis, Dept. of E.E. Washington Univ. St. Louis (May 1982)
• 2: Benes, V.E. MATHEMATICAL THOERY OF CONNECTING NETWORKS AND TELEPHONE TRAFFIC, Acad. Press, N.Y. (1965)
• 3: Clark, W.A. Macromodular Computer Systems, AFIPS Proc. SJCC (Apr 1967)
• 4: Jack B. Dennis , David P. Misunas, A preliminary architecture for a basic data-flow processor, Proceedings of the 2nd annual symposium on Computer architecture, p.126-132, January 20-22, 1975
• 5: Digital Equipment Corp, MICROCOMPUTERS AND MEMORIES, DEC, Maynard, Mass (1981)
• 6: Fang, T.P. On the Design of Hazard Free Circuits, Computer Sys. Lab., T.M. 285, Washington Univ., St. Louis (Nov 81)
• 7: M. A. Franklin , S. A. Kahn , M. J. Stucki, Design issues in the development of a modular multiprocessor communications network, Proceedings of the 6th annual symposium on Computer architecture, p.182-187, April 23-25, 1979 [doi>10.1145/800090.802908]
• 8: Franklin, M.A. and Wann, D.F. Pin Limitations and VLSI Interconnection Networks, Proc. 1981 Conf. on Parallel Processing (1981)
• 9: Franklin, M.A. VLSI Performance Comparison of Banyan and Crossbar Switching Networks, IEEE Trans. Comp. C-30, 4 (Apr 1981)
• 10: Franklin, M.A., Wann, D.F. and Thomas, W.J. Word Inconsistency in Partitioned VLSI Interconnection Networks, Center for Computer Systems Design TM 81FR-B, Washington Univ. St. Louis (1981)
• 11: L. Rodney Goke , G. J. Lipovski, Banyan networks for partitioning multiprocessor systems, Proceedings of the 1st annual symposium on Computer architecture, p.21-28, December 09-11, 1973
• 12: Hoey, D. and Leiserson, C.E. A Layout for the Shuffle-Exchange Network, Proc. Inter. Conf. on Parallel Processing (1980)
• 13: Lawrie, D. H. Access and Alignment of Data in an Array Processor, IEEE Trans. Comp. C-24, 12 (Dec 1975)
• 14: Malek, M and Myres, W.W. Figures of Merit for Interconnection Networks, Proc. Workshop on Interconnection Ntwks. Purdue Univ. (Apr 1980)
• 15: Carver Mead , Lynn Conway, Introduction to VLSI Systems, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1979
• 16: Padmanabhan, K. Multiprocessor Interconnection Networks in a VLSI Environment, M.S. Thesis, Dept. of E.E., Washington Univ., St. Louis (Dec 1981)
• 17: Janak H. Patel, Processor-memory interconnections for multiprocessors, Proceedings of the 6th annual symposium on Computer architecture, p.168-177, April 23-25, 1979 [doi>10.1145/800090.802906]
• 18: Pease, M.C. The Indirect Binary n-Cube Microprocessor Array, IEEE Trans. Comp. C-26,5 (May 1977)
• 19: Quatember, B. Modular Crossbar Switch for Large Scale Multiprocessor Systems - Structure and Implementation, AFIPS Proc. Nat. Comp. Conf. (1981)
• 20: Seitz, C.L. Self-Timed VLSI Systems, Proc. Caltech., Conf. on VLSI. (Jan 1979)
• 21: Seitz, C.L. System Timing, Chapter 7 in INTRODUCTION TO VLSI SYSTEMS by Mead, C. and Conway, L., Addison-Wesley, Reading, Mass. (1980)
• 22: Sejnowski, M.C., et.al. An Overview of the Texas Reconfigurable Computer, AFIPS Proc., Nat. Comp. Conf. (1980)
• 23: Siegel, H.J. A Survey of Interconnection Methods for Reconfigurable Parallel Processing Systems, AFIPS Proc., Nat. Comp. Conf. (June 1979)
• 24: Herbert Sullivan , T R Bashkow, A large scale, homogeneous, fully distributed parallel machine, I, Proceedings of the 4th annual symposium on Computer architecture, p.105-117, March 23-25, 1977
• 25: Sutherland, I.E., et.al. The TRIMOSBUS, Proc. Caltech. Conf. on VLSI, (Jan 1979)
• 26: Swan, R.J. et.al. Cm* - A Modular Multi-Microprocessor, AFIPS Proc. Nat. Comp. Conf. (1977)
• 27: Thompson, C.D. A Complexity Theory for VLSI, Proc. 11th Ann. ACM Symp. on Theory of Computing (Apr 1979)

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Asynchronous/synchronous operation

General Terms:
Design