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RISC assessment: A high-level language experiment
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Source International Symposium on Computer Architecture archive
Proceedings of the 9th annual symposium on Computer Architecture table of contents
Austin, Texas, United States
Pages: 3 - 8  
Year of Publication: 1982
Also published in ...
Authors
David A. Patterson  Computer Science Division, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, California
Richard S. Piepho  Bell Laboratories, Naiperville, Illinois
Sponsors
IEEE-CS : Computer Society
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
Bibliometrics
Downloads (6 Weeks): 20,   Downloads (12 Months): 34,   Citation Count: 7
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

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ABSTRACT

We present the result of an informal experiment comparing the performance of one Reduced Instruction Set Computer, RISC I, to five traditional computers, VAX-11/780, PDP-11/70, BBN C/70, MC68000, and Z8000, in a high-level language environment. Measuring either absolute performance or the penalty for using high-level languages, the best computer is RISC I.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Fitzpatrick, D.T., Foderaro, J.K., Katevenis, M.G.H., Landman, H.A., Patterson, D.A., Peek, J.B., and Peshkess, Z., "VLSI Implementations of a Reduced Instruction Set Computer," Proc. CMU Conference on VLSI Systems and Computations, pp. 327-336 (October 19-21, 1981).
 
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Fitzpatrick, D.T., Foderaro, J.K., Katevenis, M.G.H., Landman, H.A., Patterson, D.A., Peek, J.B., Peshkess, Z., S&eactue;quin, C.H., Sherburne, R.W., and Van Dyke, K.S., "A RISCy Approach to VLSI," VLSI DesignII(4) pp. 14-20 (Fourth Quarter (October, 1981)).
 
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Collaborative Colleagues:
David A. Patterson: colleagues
Richard S. Piepho: colleagues