The design of bit-parallel systolic filter algorithms

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The design of bit-parallel systolic filter algorithms

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ACM Annual Computer Science Conference archive
Proceedings of the ACM 12th annual computer science conference on SIGCSE symposium table of contents

Philadelphia, Pennsylvania

Pages: 121 - 130

Year of Publication: 1984

ISBN:0-89791-127-X

Author

Paul L. Mills

Sponsor

ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 3, Citation Count: 1

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ABSTRACT

In this paper we present a methodology for the design of systolic arrays for numeric and non-numeric (symbolic) systolic functions. This methodology is then applied to the Finite Impulse Response (F.I.R) Filter function. A particular design approach is followed and we present the complete design procedure and specification for a two-stage, two-bit input data and two-bit reference coefficient bit parallel filter.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	KUNG. H.T. and LEISERSON. C. E. - 'Algorithms for VLSI processor Arrays' in Introduction to VLSI Systems, MEAD. C. and CONWAY. L. edts, Addison-Wesley, 1980.
	2	BAUGH and WOOLEY - 'A Two's Complement Parallel Array Multiplication Algorithm' in IEEE Trans Computers Vol C-22 No 1-2 pp 1045-1047. December 1973.