An Event-Driven Multi-Threading Architecture for Embedded Systems

ABSTRACT

In this paper we present an event driven multi-threading architecture and its underlying event flow system model of computation as a framework for the implementation of complex reactive and communication systems. Existing process oriented specification languages can be used to specify the system and embedded in the model. The target architecture covers a wide variety of architectures, varying from small FSMs to large processors, which are interconnected by a network template which performs dynamic scheduling and communication for different levels of process granularity and timing. Interconnect and module implementation and optimization is based on an event flow graph model (EFG). In this paper we present our system model and the architectural template and show how they can be applied to an industrial application example.

REFERENCES

• 1: [1] Motorola: 'TPU - Time Processing Unit Refernce Manual', 1990.
• 2: R. Gerndt, A Case Study in Co-Design of Communication Controllers, Proceedings of the 4th International Workshop on Hardware/Software Co-Design, p.104, March 18-20, 1996
• 3: Nicolas Halbwachs, Synchronous Programming of Reactive Systems, Kluwer Academic Publishers, Norwell, MA, 1992
• 4: [4] R. Kumar, V. K. Garg: 'Modeling and Control of Logical Discrete Event Systems', Kluwer Academic Publishers, 1995.
• 5: [5] M. Rudert: 'Entwicklung einer Entwurfssystematik am Beispiel der FPGA-Implementierung eines Feldbus-Moduls', Diplomarbeit, Fachhochschule Braunschweig-Wolfenbüttel ('Application of a Design Method to an FPGA Implementation of a Fieldbus Module', Master Thesis, Fachhochschule Braunschweig-Wolfenbüttel).
• 6: James Lyle Peterson, Petri Net Theory and the Modeling of Systems, Prentice Hall PTR, Upper Saddle River, NJ, 1981
• 7: [7] Siemens: 'Microcomputer Components', User's Manual 6.90.
• 8: [8] EN 50170, European Fieldbus Standard.

INDEX TERMS

Keywords:
event-flow, embedded system, hardware/software-codesign, multi-threading architecture