Contention is no obstacle to shared-memory multiprocessing

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Contention is no obstacle to shared-memory multiprocessing

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Communications of the ACM archive
Volume 29 , Issue 12 (December 1986) table of contents
Special issue on parallelism

Pages: 1202 - 1212

Year of Publication: 1986

ISSN:0001-0782

Authors

Randall Rettberg	BBN Advanced Computers, Cambridge, MA
Robert Thomas	BBN Advanced Computers, Cambridge, MA

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 27, Citation Count: 20

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abstract references cited by index terms review collaborative colleagues

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ABSTRACT

Contention in large-scale shared-memory systems is less of a concern than generally believed. Through careful engineering of a parallel system, the effects of contention can be controlled.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	BBN Advanced Computers. Quarterly technical report no. 3 April l&July 15. 1984 development of a Butterfly multiprocessor test bed: The Butterfly switch. Tech. Rep. 5874, BBN Advanced Computers, Cambridge, Mass.. Oct. 1985, pp. 15-21.
	2	BBN Advanced Computers. The Uniform System approach to programming the Butterfly parallel processor. Rep. 6149, Version 2, BBN Advanced Computers, Cambridge. Mass., June 1986. pp. 3-5.
	3	Gottlieb, A., Grishman, R.. Kruskal, C.P., McAuliffe. K.M., Rudolph, L., and Snir, M. The NYU ultracomputer-Designing an MIMD shared memory parallel computer. IEEE Tram. Compuf. C-32, 2 (1983). 175-189.
	4	Rosanna Lee, On “hot spot” contention, ACM SIGARCH Computer Architecture News, v.13 n.5, p.15-20, Dec 1 1985 [doi>10.1145/381757.381759]
	5	Pfister, G.F., and Norton, V.A. "Hot spot" contention and combining in multistage interconnection networks. In Proceedings offhe 1985 Inferrfafiotul Cortference on Parallel Processing (Aug.). IEEE Press, New York. 1985. pp. 790-797.
	6	Thomas, R. Behavior of the Butterfly" parallel processor in the presence of memory hot spots. In Proceedings of f/w 1986 International Cor~ferure o)! Parafkl Processiq (St. Charles. Ill., Aug 19-22). IEEE Press. New York, 1986. pp. 46-50.
	7	Thomas, R., Crowther, W.. and Gurwitz, R. Benchmark results for a 256-node Butterly" parallel processor. Rep. 6355, BBN Laboratories, Cambridge, Mass., Aug. 1986.
	8	Yew, PC., Tzeng, N.S., and Law&, D.H. Distributing hot spot addressing in large-scale multiprocessors. In Proceedings of the 1986 Infert~atiortal Couferet~ce on Parallel Processing (St. Charles, 111.. Aug. 19-22). IEEE Press, New York, 1986, pp. 51-58.

CITED BY 20

	Thomas J. LeBlanc , Michael L. Scott , Christopher M. Brown, Large-scale parallel programming: experience with BBN butterfly parallel processor, ACM SIGPLAN Notices, v.23 n.9, p.161-172, Sept. 1988
	J. F. Pekny , D. L. Miller, An exact parallel algorithm for the resource constrained traveling salesman problem with application to scheduling with an aggregate deadline, Proceedings of the 1990 ACM annual conference on Cooperation, p.208-214, February 20-22, 1990, Washington, D.C., United States
	D. E. Marquardt , H. S. Alkhatib, C²MP: a cache-coherent, distributed memory multiprocessor-system, Proceedings of the 1989 ACM/IEEE conference on Supercomputing, p.466-475, November 12-17, 1989, Reno, Nevada, United States
	Clyde P. Kruskal , Larry Rudolph , Marc Snir, Efficient synchronization of multiprocessors with shared memory, ACM Transactions on Programming Languages and Systems (TOPLAS), v.10 n.4, p.579-601, Oct. 1988
	Roger E. Eggen , John R. Metzner, An inherently parlle large grained data flow environment, Proceedings of the 1988 ACM sixteenth annual conference on Computer science, p.551-557, February 1988, Atlanta, Georgia, United States
	Darryl L. Willick , D. L. Eager, An analytic model of multistage interconnection networks, ACM SIGMETRICS Performance Evaluation Review, v.18 n.1, p.192-202, May 1990
	Jeremy Brown , J. P. Grossman , Tom Knight, A lightweight idempotent messaging protocol for faulty networks, Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures, August 10-13, 2002, Winnipeg, Manitoba, Canada
	Akira Fukuda , Kazuaki Murakami , Shinji Tomita, Toward Advanced Parallel Processing: Exploiting Parallelism at Task and Instruction Levels, IEEE Micro, v.11 n.4, p.16-19, 50-61, July 1991
	Lionel M. Ni , Ching-Farn E. Wu, Design Tradeoffs for Process Scheduling in Shared Memory Multiprocessor Systems, IEEE Transactions on Software Engineering, v.15 n.3, p.327-334, March 1989
	J. F. Pekny , D. L. Miller, A parallel branch and bound algorithm for solving large asymmetric traveling salesman problems, Proceedings of the 1990 ACM annual conference on Cooperation, p.56-62, February 20-22, 1990, Washington, D.C., United States
	Egon Balas , Donald Miller , Joseph Pekny , Paolo Toth, A parallel shortest augmenting path algorithm for the assignment problem, Journal of the ACM (JACM), v.38 n.4, p.985-1004, Oct. 1991
	John B. Gilmer, Jr. , David W. O'Brien , Jeffery E. Payne, Toward real time simulation: prototyping of a large scale parallel ground target simulation, Proceedings of the 22nd conference on Winter simulation, p.870-877, December 09-12, 1990, New Orleans, Louisiana, United States
	P. Heidelberger , A. Norton , John T. Robinson, Parallel Quicksort Using Fetch-And-Add, IEEE Transactions on Computers, v.39 n.1, p.133-138, January 1990
	Randall D. Rettberg , William R. Crowther , Philip P. Carvey , Raymond S. Tomlinson, The Monarch Parallel Processor Hardware Design, Computer, v.23 n.4, p.18-28, 30, April 1990
	W. Lin , T.-L. Sheu , C. R. Das , T.-Y. Feng , C.-L. Wu, A Conflict-Free Routing Scheme on Multistage Interconnection Networks, IEEE Transactions on Computers, v.38 n.8, p.1086-1097, August 1989
	S. Wei , G. Lee, Extra group network: a cost-effective fault-tolerant multistage interconnection network, ACM SIGARCH Computer Architecture News, v.16 n.2, p.108-115, May 1988
	James R. Larus, Compiling for shared-memory and message-passing computers, ACM Letters on Programming Languages and Systems (LOPLAS), v.2 n.1-4, p.165-180, March–Dec. 1993
	Sanjiv K. Bhatia , A. G. Starling, Multilayered illiac network scheme, ACM SIGARCH Computer Architecture News, v.15 n.4, p.23-31, September 1, 1987
	Edward Gehringer , Janne Abullarade , Michael H. Gulyn, A survey of commercial parallel processors, ACM SIGARCH Computer Architecture News, v.16 n.4, p.75-107, Sept. 1988
	A. Aggarwal , A. K. Chandra , M. Snir, On communication latency in PRAM computations, Proceedings of the first annual ACM symposium on Parallel algorithms and architectures, p.11-21, June 18-21, 1989, Santa Fe, New Mexico, United States

INDEX TERMS

Classification:
B. Hardware
B.3 MEMORY STRUCTURES

C. Computer Systems Organization
C.1 PROCESSOR ARCHITECTURES

General Terms:
Design, Performance

REVIEW

"Nigel Peter Topham : Reviewer"

This paper, by two employees of BBN, discusses the implications of using a shared-memory architecture in a multiple multiprocessor system. The general claim, for which convincing experimental results are presented, is that contention is less of more...

Collaborative Colleagues:

Randall Rettberg: colleagues

Robert Thomas: colleagues

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