Address code generation for DSP instruction-set architectures

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Address code generation for DSP instruction-set architectures

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ACM Transactions on Design Automation of Electronic Systems (TODAES) archive
Volume 8 , Issue 3 (July 2003) table of contents

Pages: 384 - 395

Year of Publication: 2003

ISSN:1084-4309

Authors

J.-Y. Lee	Hynix Semiconductor, Inc., Republic of Korea
I.-C. Park	Korea Advanced Institute of Science and Technology, Republic of Korea

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 42, Citation Count: 2

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ABSTRACT

This paper presents a new DSP-oriented code optimization method to enhance performance by exploiting the specific architectural features of digital signal processors. In the proposed method, a source code is translated into the static single assignment form while preserving the high-level information related to the address computation of array accesses. The information is used in generating auto-modification addressing operations provided by most digital signal processors. In addition to the conventional control-data flow graph, a new graph is employed to find auto-modification addressing modes efficiently. Experimental results on benchmark programs show that the proposed method is effective in improving performance and reducing code size.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 2

	O. Ozturk , M. Kandemir , S. Tosun, An ILP based approach to address code generation for digital signal processors, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Guilin Chen , Mahmut Kandemir, Optimizing Address Code Generation for Array-Intensive DSP Applications, Proceedings of the international symposium on Code generation and optimization, p.141-152, March 20-23, 2005