| Efficient description of the design space of analog circuits |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 40th annual Design Automation Conference
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Anaheim, CA, USA
SESSION: Analog design space exploration
table of contents
Pages: 970 - 973
Year of Publication: 2003
ISBN:1-58113-688-9
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Downloads (6 Weeks): 6, Downloads (12 Months): 24, Citation Count: 5
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ABSTRACT
In this paper we present a method for determining the feasible set of analog design problems and we propose an efficient method for their verification. The verification method presented relies on the formulation of the analog circuit design problem as a convex optimization problem in both the design variables and the performance specifications. Since the design is convex not only in the design variables but also in the specification parameters, we observe that the feasible sets are convex and points at the boundary can be found by solving a single convex optimization problem. We also show that feasible sets can be very well approximated with a polyhedron and therefore defined by a finite set of points. The implication of the latter is that new verifications do not need to be run for every new instantiation of a synthesized analog cell.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 5
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Daniel Mueller , Guido Stehr , Helmut Graeb , Ulf Schlichtmann, Deterministic approaches to analog performance space exploration (PSE), Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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Jun Zou , Daniel Mueller , Helmut Graeb , Ulf Schlichtmann, A CPPLL hierarchical optimization methodology considering jitter, power and locking time, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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Xin Li , Jian Wang , L. T. Pileggi , Tun-Shih Chen , Wanju Chiang, Performance-centering optimization for system-level analog design exploration, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.422-429, November 06-10, 2005, San Jose, CA
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