Performance trade-off analysis of analog circuits by normal-boundary intersection

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Performance trade-off analysis of analog circuits by normal-boundary intersection

Full text

Pdf (203 KB)

Source

Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th annual Design Automation Conference table of contents

Anaheim, CA, USA

SESSION: Analog design space exploration table of contents

Pages: 958 - 963

Year of Publication: 2003

ISBN:1-58113-688-9

Authors

Guido Stehr	University of Munich, Munich, Germany
Helmut Graeb	University of Munich, Munich, Germany
Kurt Antreich	University of Munich, Munich, Germany

Sponsor

ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 37, Citation Count: 16

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/775832.776073 What is a DOI?

ABSTRACT

We present a new technique to examine the trade-off regions of a circuit where its competing performances become "simultaneously optimal", i.e. Pareto optimal. It is based on circuit simulation, sizing rules, which capture elementary topological and technological constraints, and an advanced multicriteria optimization formulation called normal-boundary intersection. We are able to efficiently calculate a well-balanced discretization of a Pareto surface, identify the active constraints, which prevent a further improvement, and even rank these constraints in terms of stringency. Experimental results demonstrate the efficacy and efficiency of the method and its potential for topology selection and analog synthesis.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Indraneel Das , J. E. Dennis, Normal-Boundary Intersection: A New Method for Generating the Pareto Surface in Nonlinear Multicriteria Optimization Problems, SIAM Journal on Optimization, v.8 n.3, p.631-657, 1998 [doi>10.1137/S1052623496307510]
	2	B. De Smedt and G. G. E. Gielen. WATSON: Design space boundary exploration and model generation for analog and RF IC design. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 22(2):213--223, Feb. 2003.
	3	Kalyanmoy Deb , Deb Kalyanmoy, Multi-Objective Optimization Using Evolutionary Algorithms, John Wiley & Sons, Inc., New York, NY, 2001
	4	M. del Mar~Hershenson, S. P. Boyd, and T. H. Lee. Optimal design of a CMOS Op-Amp via geometric programming. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 20(1):1--21, Jan. 2001.
	5	R. Fletcher, Practical methods of optimization; (2nd ed.), Wiley-Interscience, New York, NY, 1987
	6	H. Graeb , S. Zizala , J. Eckmueller , K. Antreich, The sizing rules method for analog integrated circuit design, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	7	Ramesh Harjani , Jianfeng Shao, Feasibility and performance region modeling of analog and digital circuits, Analog Integrated Circuits and Signal Processing, v.10 n.1-2, p.23-43, June/July 1996 [doi>10.1007/BF00713977]
	8	M. Lightner, T. Trick, and R. Zug. Circuit optimization and design. Circuit Analysis, Simulation and Design, Part 2 (A. Ruehli). Advances in CAD for VLSI 3, pages 333--391, 1987.
	9	G. Van der Plas, G. Debyser, F. Leyn, K. Lampaert, J. Vandenbussche, G. Gielen, W. Sansen, P. Veselinovic, and D. Leenaerts. AMGIE--A synthesis environment for CMOS analog integrated circuits. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 20(9):1037--1058, Sept. 2001.

CITED BY 16

	Georges Gielen , Trent McConaghy , Tom Eeckelaert, Performance space modeling for hierarchical synthesis of analog integrated circuits, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Daniel Mueller , Guido Stehr , Helmut Graeb , Ulf Schlichtmann, Deterministic approaches to analog performance space exploration (PSE), Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Arthur Nieuwoudt , Tamer Ragheb , Yehia Massoud, SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Saurabh K. Tiwary , Pragati K. Tiwary , Rob A. Rutenbar, Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Guo Yu , Peng Li, Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Daniel Mueller , Helmut Graeb , Ulf Schlichtmann, Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	G. Stehr , H. Graeb , K. Antreich, Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.847-854, November 07-11, 2004
	Julia Handl , Douglas B. Kell , Joshua Knowles, Multiobjective Optimization in Bioinformatics and Computational Biology, IEEE/ACM Transactions on Computational Biology and Bioinformatics (TCBB), v.4 n.2, p.279-292, April 2007
	Xin Li , Jian Wang , L. T. Pileggi , Tun-Shih Chen , Wanju Chiang, Performance-centering optimization for system-level analog design exploration, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.422-429, November 06-10, 2005, San Jose, CA
	Yu-Tsun Chien , Dong Chen , Jea-Hong Lou , Gin-Kou Ma , Rob A. Rutenbar , Tamal Mukherjee, Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters, Proceedings of the conference on Design, Automation and Test in Europe, p.279-280, March 07-11, 2005
	Abhishek Somani , P. P. Chakrabarti , Amit Patra, Mixing Global and Local Competition in Genetic Optimization based Design Space Exploration of Analog Circuits, Proceedings of the conference on Design, Automation and Test in Europe, p.1064-1069, March 07-11, 2005
	Arthur Nieuwoudt , Tamer Ragheb , Yehia Massoud, Narrow-band low-noise amplifier synthesis for high-performance system-on-chip design, Microelectronics Journal, v.38 n.12, p.1123-1134, December, 2007
	Chenjie Gu , Jaijeet Roychowdhury, An efficient, fully nonlinear, variability-aware non-Monte-Carlo yield estimation procedure with applications to SRAM cells and ring oscillators, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Sawal Ali , Reuben Wilcock , Peter Wilson , Andrew Brown, A new approach for combining yield and performance in behavioural models for analogue integrated circuits, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Guo Yu , Peng Li, Yield-aware hierarchical optimization of large analog integrated circuits, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Yu Liu , Masato Yoshioka , Katsumi Homma , Toshiyuki Shibuya, Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan