| Post-route gate sizing for crosstalk noise reduction |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 40th annual Design Automation Conference
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Anaheim, CA, USA
SESSION: Interconnect noise avoidance methodologies & slew rate prediction
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Pages: 954 - 957
Year of Publication: 2003
ISBN:1-58113-688-9
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Downloads (6 Weeks): 2, Downloads (12 Months): 10, Citation Count: 5
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ABSTRACT
Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic post-route gate sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several industrial high performance designs.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Buffer insertion for noise and delay optimization, Proceedings of the 35th annual conference on Design automation, p.362-367, June 15-19, 1998, San Francisco, California, United States
[doi> 10.1145/277044.277145]
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Rafi Levy , David Blaauw , Gabi Braca , Aurobindo Dasgupta , Amir Grinshpon , Chanlee Oh , Boaz Orshav , Supamas Sirichotiyakul , Vladimir Zolotov, ClariNet: a noise analysis tool for deep submicron design, Proceedings of the 37th conference on Design automation, p.233-238, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337400]
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