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Post-route gate sizing for crosstalk noise reduction
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th annual Design Automation Conference table of contents
Anaheim, CA, USA
SESSION: Interconnect noise avoidance methodologies & slew rate prediction table of contents
Pages: 954 - 957  
Year of Publication: 2003
ISBN:1-58113-688-9
Authors
Murat R. Becer  Motorola Inc.
David Blaauw  Univ. of Michigan, Ann Arbor, MI
Ilan Algor  Motorola Inc.
Rajendran Panda  Motorola Inc.
Chanhee Oh  Motorola Inc.
Vladimir Zolotov  Motorola Inc.
Ibrahim N. Hajj  University of Illinois Urbana-Champaign
Sponsor
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 2,   Downloads (12 Months): 10,   Citation Count: 5
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ABSTRACT

Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic post-route gate sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several industrial high performance designs.


REFERENCES

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Collaborative Colleagues:
Murat R. Becer: colleagues
David Blaauw: colleagues
Ilan Algor: colleagues
Rajendran Panda: colleagues
Chanhee Oh: colleagues
Vladimir Zolotov: colleagues
Ibrahim N. Hajj: colleagues