Statistical timing for parametric yield prediction of digital integrated circuits

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Statistical timing for parametric yield prediction of digital integrated circuits

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th annual Design Automation Conference table of contents

Anaheim, CA, USA

SESSION: Budgeting, simulation and statistical timing table of contents

Pages: 932 - 937

Year of Publication: 2003

ISBN:1-58113-688-9

Authors

J. A. G. Jess	Eindhoven University of Technology, Eindhoven, The Netherlands
K. Kalafala	IBM Microelectronics Division, East Fishkill, NY
S. R. Naidu	Eindhoven University of Technology, Eindhoven, The Netherlands
R. H. J. M. Otten	Eindhoven University of Technology, Eindhoven, The Netherlands
C. Visweswariah	IBM Thomas J. Watson Research Center, Yorktown Heights, NY

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ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 9, Downloads (12 Months): 36, Citation Count: 38

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ABSTRACT

Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Across-the-chip variability continues to be accommodated by EinsTimer's "Linear Combination of Delay (LCD)" mode. Timing analysis results in the face of statistical temperature and V_dd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results.

REFERENCES

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